From 1db4135e32e03c0131301ed46d906a2bf8f08c9b Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Tue, 7 Feb 2017 16:19:18 +0100 Subject: cns3xxx: add preliminary 4.9 support Adds preliminary kernel 4.9 support for this target. - Refreshed/Updated all patches Added 3 new patches: - 093 --> Add virtual PCI MMIO mapping - 230 --> Remove deprecated code - 240 --> Rework AT24 eeprom code to use the new NVMEM API Compiled & tested on cns3xxx (gw2388) Signed-off-by: Koen Vandeputte --- .../cns3xxx/patches-4.9/095-gpio_support.patch | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 target/linux/cns3xxx/patches-4.9/095-gpio_support.patch (limited to 'target/linux/cns3xxx/patches-4.9/095-gpio_support.patch') diff --git a/target/linux/cns3xxx/patches-4.9/095-gpio_support.patch b/target/linux/cns3xxx/patches-4.9/095-gpio_support.patch new file mode 100644 index 0000000000..bf896b48c8 --- /dev/null +++ b/target/linux/cns3xxx/patches-4.9/095-gpio_support.patch @@ -0,0 +1,67 @@ +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -245,6 +245,10 @@ static void __init cns3420_init(void) + + cns3xxx_ahci_init(); + cns3xxx_sdhci_init(); ++ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, ++ NR_IRQS_CNS3XXX); ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, ++ NR_IRQS_CNS3XXX + 32); + + pm_power_off = cns3xxx_power_off; + } +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -2,6 +2,8 @@ menuconfig ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" + depends on ARCH_MULTI_V6 + select ARM_GIC ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_IRQ_CHIP + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD + select HAVE_SMP +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,7 +1,7 @@ + ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include + + obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o +-cns3xxx-y += core.o pm.o ++cns3xxx-y += core.o pm.o gpio.o + cns3xxx-$(CONFIG_ATAGS) += devices.o + cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +--- a/arch/arm/mach-cns3xxx/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/cns3xxx.h +@@ -68,8 +68,10 @@ + #define SMC_PCELL_ID_3_OFFSET 0xFFC + + #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ ++#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000 + + #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ ++#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000 + + #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ + +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), + .length = SZ_4K, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_GPIOA_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_GPIOB_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, + #ifdef CONFIG_PCI + }, { + .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, -- cgit v1.2.3