From ebf6331c10774ebc3ef70b0598871bcd42ac7417 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 26 Nov 2014 18:01:38 +0000 Subject: cns3xxx: switch to using the upstream dwc2 driver instead of dwc_otg Signed-off-by: Felix Fietkau SVN-Revision: 43398 --- .../cns3xxx/patches-3.14/100-laguna_support.patch | 46 +++++ .../101-laguna_sdhci_card_detect.patch | 16 ++ .../patches-3.14/110-pci_isolated_interrupts.patch | 193 +++++++++++++++++++++ .../patches-3.14/200-broadcom_phy_reinit.patch | 14 ++ .../cns3xxx/patches-3.14/200-dwc_otg_support.patch | 48 ----- .../cns3xxx/patches-3.14/210-dwc2_defaults.patch | 47 +++++ .../cns3xxx/patches-3.14/300-laguna_support.patch | 46 ----- .../305-laguna_sdhci_card_detect.patch | 16 -- .../patches-3.14/310-pci_isolated_interrupts.patch | 193 --------------------- .../patches-3.14/400-broadcom_phy_reinit.patch | 14 -- 10 files changed, 316 insertions(+), 317 deletions(-) create mode 100644 target/linux/cns3xxx/patches-3.14/100-laguna_support.patch create mode 100644 target/linux/cns3xxx/patches-3.14/101-laguna_sdhci_card_detect.patch create mode 100644 target/linux/cns3xxx/patches-3.14/110-pci_isolated_interrupts.patch create mode 100644 target/linux/cns3xxx/patches-3.14/200-broadcom_phy_reinit.patch delete mode 100644 target/linux/cns3xxx/patches-3.14/200-dwc_otg_support.patch create mode 100644 target/linux/cns3xxx/patches-3.14/210-dwc2_defaults.patch delete mode 100644 target/linux/cns3xxx/patches-3.14/300-laguna_support.patch delete mode 100644 target/linux/cns3xxx/patches-3.14/305-laguna_sdhci_card_detect.patch delete mode 100644 target/linux/cns3xxx/patches-3.14/310-pci_isolated_interrupts.patch delete mode 100644 target/linux/cns3xxx/patches-3.14/400-broadcom_phy_reinit.patch (limited to 'target/linux/cns3xxx/patches-3.14') diff --git a/target/linux/cns3xxx/patches-3.14/100-laguna_support.patch b/target/linux/cns3xxx/patches-3.14/100-laguna_support.patch new file mode 100644 index 0000000000..d2338e23d1 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.14/100-laguna_support.patch @@ -0,0 +1,46 @@ +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -27,4 +27,12 @@ config MACH_CNS3420VB + This is a platform with an on-board ARM11 MPCore and has support + for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. + ++config MACH_GW2388 ++ bool "Support for Gateworks Laguna Platform" ++ help ++ Include support for the Gateworks Laguna Platform ++ ++ This is a platform with an on-board ARM11 MPCore and has support ++ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc. ++ + endmenu +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o + cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o + cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o ++cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o ++ +--- a/arch/arm/mach-cns3xxx/devices.c ++++ b/arch/arm/mach-cns3xxx/devices.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include "cns3xxx.h" + #include "pm.h" + #include "core.h" +@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void) + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ +- gpioa_pins |= 0x1fff0004; ++ if (machine_is_gw2388()) { ++ gpioa_pins |= 0x1fff0000; ++ } else { ++ gpioa_pins |= 0x1fff0004; ++ } + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); diff --git a/target/linux/cns3xxx/patches-3.14/101-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-3.14/101-laguna_sdhci_card_detect.patch new file mode 100644 index 0000000000..2d287851bc --- /dev/null +++ b/target/linux/cns3xxx/patches-3.14/101-laguna_sdhci_card_detect.patch @@ -0,0 +1,16 @@ +--- a/drivers/mmc/host/sdhci-cns3xxx.c ++++ b/drivers/mmc/host/sdhci-cns3xxx.c +@@ -88,10 +88,11 @@ static const struct sdhci_pltfm_data sdh + .ops = &sdhci_cns3xxx_ops, + .quirks = SDHCI_QUIRK_BROKEN_DMA | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | +- SDHCI_QUIRK_INVERTED_WRITE_PROTECT | ++ //SDHCI_QUIRK_INVERTED_WRITE_PROTECT | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | +- SDHCI_QUIRK_NONSTANDARD_CLOCK, ++ SDHCI_QUIRK_NONSTANDARD_CLOCK | ++ SDHCI_QUIRK_BROKEN_CARD_DETECTION, + }; + + static int sdhci_cns3xxx_probe(struct platform_device *pdev) diff --git a/target/linux/cns3xxx/patches-3.14/110-pci_isolated_interrupts.patch b/target/linux/cns3xxx/patches-3.14/110-pci_isolated_interrupts.patch new file mode 100644 index 0000000000..3e4cc67979 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.14/110-pci_isolated_interrupts.patch @@ -0,0 +1,193 @@ +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -274,7 +274,7 @@ static int __init cns3420vb_pcie_init(vo + if (!machine_is_cns3420vb()) + return 0; + +- return cns3xxx_pcie_init(); ++ return cns3xxx_pcie_init(NULL, NULL); + } + subsys_initcall(cns3420vb_pcie_init); + +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -19,7 +19,7 @@ extern void cns3xxx_pcie_iotable_init(vo + + void __init cns3xxx_map_io(void); + void __init cns3xxx_init_irq(void); +-int __init cns3xxx_pcie_init(void); ++int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs); + void cns3xxx_power_off(void); + void cns3xxx_restart(enum reboot_mode, const char *); + +--- a/arch/arm/mach-cns3xxx/laguna.c ++++ b/arch/arm/mach-cns3xxx/laguna.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -868,12 +869,42 @@ static int laguna_register_gpio(struct g + return ret; + } + ++/* allow disabling of external isolated PCIe IRQs */ ++static int cns3xxx_pciextirq = 1; ++static int __init cns3xxx_pciextirq_disable(char *s) ++{ ++ cns3xxx_pciextirq = 0; ++ return 1; ++} ++__setup("noextirq", cns3xxx_pciextirq_disable); ++ + static int __init laguna_pcie_init(void) + { ++ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004); ++ u32 reg = (__raw_readl(mem) >> 26) & 0xf; ++ int irqs[] = { ++ IRQ_CNS3XXX_EXTERNAL_PIN0, ++ IRQ_CNS3XXX_EXTERNAL_PIN1, ++ IRQ_CNS3XXX_EXTERNAL_PIN2, ++ 154, ++ }; ++ + if (!machine_is_gw2388()) + return 0; + +- return cns3xxx_pcie_init(); ++ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */ ++ if (cns3xxx_pciextirq && reg != 1) ++ cns3xxx_pciextirq = 0; ++ ++ if (cns3xxx_pciextirq) { ++ printk("laguna: using isolated PCI interrupts:" ++ " irq%d/irq%d/irq%d/irq%d\n", ++ irqs[0], irqs[1], irqs[2], irqs[3]); ++ return cns3xxx_pcie_init(irqs, NULL); ++ } ++ printk("laguna: using shared PCI interrupts: irq%d\n", ++ IRQ_CNS3XXX_PCIE0_DEVICE); ++ return cns3xxx_pcie_init(NULL, NULL); + } + subsys_initcall(laguna_pcie_init); + +@@ -888,8 +919,33 @@ static int __init laguna_model_setup(voi + printk("Running on Gateworks Laguna %s\n", laguna_info.model); + cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, + NR_IRQS_CNS3XXX); +- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, +- NR_IRQS_CNS3XXX + 32); ++ ++ /* ++ * If pcie external interrupts are supported and desired ++ * configure IRQ types and configure pin function. ++ * Note that cns3xxx_pciextirq is enabled by default, but can be ++ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if ++ * the baseboard model does not support this hardware feature. ++ */ ++ if (cns3xxx_pciextirq) { ++ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018); ++ reg = __raw_readl(mem); ++ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */ ++ reg &= ~0x3c000000; ++ reg |= 0x38000000; ++ __raw_writel(reg, mem); ++ ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, ++ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); ++ ++ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH); ++ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH); ++ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH); ++ } else { ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, ++ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); ++ } + + if (strncmp(laguna_info.model, "GW", 2) == 0) { + if (laguna_info.config_bitmap & ETH0_LOAD) +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + #include + #include + #include "cns3xxx.h" +@@ -32,7 +33,7 @@ enum cns3xxx_access_type { + + struct cns3xxx_pcie { + struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES]; +- unsigned int irqs[2]; ++ unsigned int irqs[6]; + struct resource res_io; + struct resource res_mem; + struct hw_pci hw_pci; +@@ -255,7 +256,7 @@ static struct pci_ops cns3xxx_pcie_ops = + static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { + struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); +- int irq = cnspci->irqs[slot]; ++ int irq = cnspci->irqs[slot+pin-1]; + + pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", + pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), +@@ -298,7 +299,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[ + .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, +- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, ++ .irqs = { IRQ_CNS3XXX_PCIE0_RC, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ }, + .hw_pci = { + .domain = 0, + .nr_controllers = 1, +@@ -340,7 +346,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[ + .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, +- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, ++ .irqs = { ++ IRQ_CNS3XXX_PCIE1_RC, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ }, + .hw_pci = { + .domain = 1, + .nr_controllers = 1, +@@ -460,13 +472,22 @@ void __init cns3xxx_pcie_iotable_init() + } + } + +-int __init cns3xxx_pcie_init(void) ++int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs) + { + int i; + + pcibios_min_io = 0; + pcibios_min_mem = 0; + ++ if (pcie0_irqs) { ++ for (i = 0; i < 4; i++) ++ cns3xxx_pcie[0].irqs[i+1] = pcie0_irqs[i]; ++ } ++ if (pcie1_irqs) { ++ for (i = 0; i < 4; i++) ++ cns3xxx_pcie[1].irqs[i+1] = pcie1_irqs[i]; ++ } ++ + hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, + "imprecise external abort"); + diff --git a/target/linux/cns3xxx/patches-3.14/200-broadcom_phy_reinit.patch b/target/linux/cns3xxx/patches-3.14/200-broadcom_phy_reinit.patch new file mode 100644 index 0000000000..bfec081fbc --- /dev/null +++ b/target/linux/cns3xxx/patches-3.14/200-broadcom_phy_reinit.patch @@ -0,0 +1,14 @@ +--- a/drivers/net/phy/broadcom.c ++++ b/drivers/net/phy/broadcom.c +@@ -567,6 +567,11 @@ static int bcm5481_config_aneg(struct ph + /* Write bits 14:0. */ + reg |= (1 << 15); + phy_write(phydev, 0x18, reg); ++ } else { ++ phy_write(phydev, 0x18, 0xf1e7); ++ phy_write(phydev, 0x1c, 0x8e00); ++ ++ phy_write(phydev, 0x1c, 0xa41f); + } + + return ret; diff --git a/target/linux/cns3xxx/patches-3.14/200-dwc_otg_support.patch b/target/linux/cns3xxx/patches-3.14/200-dwc_otg_support.patch deleted file mode 100644 index 6b9243e572..0000000000 --- a/target/linux/cns3xxx/patches-3.14/200-dwc_otg_support.patch +++ /dev/null @@ -1,48 +0,0 @@ ---- a/drivers/usb/Kconfig -+++ b/drivers/usb/Kconfig -@@ -96,6 +96,8 @@ source "drivers/usb/host/Kconfig" - - source "drivers/usb/renesas_usbhs/Kconfig" - -+source "drivers/usb/dwc/Kconfig" -+ - source "drivers/usb/class/Kconfig" - - source "drivers/usb/storage/Kconfig" ---- a/drivers/usb/core/urb.c -+++ b/drivers/usb/core/urb.c -@@ -17,7 +17,11 @@ static void urb_destroy(struct kref *kre - - if (urb->transfer_flags & URB_FREE_BUFFER) - kfree(urb->transfer_buffer); -- -+ if (urb->aligned_transfer_buffer) { -+ kfree(urb->aligned_transfer_buffer); -+ urb->aligned_transfer_buffer = 0; -+ urb->aligned_transfer_dma = 0; -+ } - kfree(urb); - } - ---- a/include/linux/usb.h -+++ b/include/linux/usb.h -@@ -1431,6 +1431,9 @@ struct urb { - unsigned int transfer_flags; /* (in) URB_SHORT_NOT_OK | ...*/ - void *transfer_buffer; /* (in) associated data buffer */ - dma_addr_t transfer_dma; /* (in) dma addr for transfer_buffer */ -+ void *aligned_transfer_buffer; /* (in) associeated data buffer */ -+ dma_addr_t aligned_transfer_dma;/* (in) dma addr for transfer_buffer */ -+ u32 aligned_transfer_buffer_length; /* (in) data buffer length */ - struct scatterlist *sg; /* (in) scatter gather buffer list */ - int num_mapped_sgs; /* (internal) mapped sg entries */ - int num_sgs; /* (in) number of entries in the sg list */ ---- a/drivers/usb/Makefile -+++ b/drivers/usb/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_USB) += core/ - - obj-$(CONFIG_USB_DWC3) += dwc3/ - obj-$(CONFIG_USB_DWC2) += dwc2/ -+obj-$(CONFIG_USB_DWC_OTG) += dwc/ - - obj-$(CONFIG_USB_MON) += mon/ - diff --git a/target/linux/cns3xxx/patches-3.14/210-dwc2_defaults.patch b/target/linux/cns3xxx/patches-3.14/210-dwc2_defaults.patch new file mode 100644 index 0000000000..00081c49b6 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.14/210-dwc2_defaults.patch @@ -0,0 +1,47 @@ +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -75,6 +75,34 @@ static const struct dwc2_core_params par + .uframe_sched = 0, + }; + ++static const struct dwc2_core_params params_cns3xxx = { ++ .otg_cap = 2, /* non-HNP/non-SRP capable */ ++ .otg_ver = 0, /* 1.3 */ ++ .dma_enable = 1, ++ .dma_desc_enable = 0, ++ .speed = 0, /* High Speed */ ++ .enable_dynamic_fifo = 1, ++ .en_multiple_tx_fifo = 1, ++ .host_rx_fifo_size = 658, /* 774 DWORDs */ ++ .host_nperio_tx_fifo_size = 128, /* 256 DWORDs */ ++ .host_perio_tx_fifo_size = 658, /* 512 DWORDs */ ++ .max_transfer_size = 65535, ++ .max_packet_count = 511, ++ .host_channels = 16, ++ .phy_type = 1, /* UTMI */ ++ .phy_utmi_width = 16, /* 8 bits */ ++ .phy_ulpi_ddr = 0, /* Single */ ++ .phy_ulpi_ext_vbus = 0, ++ .i2c_enable = 0, ++ .ulpi_fs_ls = 0, ++ .host_support_fs_ls_low_power = 0, ++ .host_ls_low_power_phy_clk = 0, /* 48 MHz */ ++ .ts_dline = 0, ++ .reload_ctl = 0, ++ .ahbcfg = 0x10, ++ .uframe_sched = 0, ++}; ++ + /** + * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the + * DWC_otg driver +@@ -134,6 +162,9 @@ static int dwc2_driver_probe(struct plat + /* Default all params to autodetect */ + dwc2_set_all_params(&defparams, -1); + params = &defparams; ++#ifdef CONFIG_ARCH_CNS3XXX ++ params = ¶ms_cns3xxx; ++#endif + } + + hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); diff --git a/target/linux/cns3xxx/patches-3.14/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.14/300-laguna_support.patch deleted file mode 100644 index d2338e23d1..0000000000 --- a/target/linux/cns3xxx/patches-3.14/300-laguna_support.patch +++ /dev/null @@ -1,46 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/Kconfig -+++ b/arch/arm/mach-cns3xxx/Kconfig -@@ -27,4 +27,12 @@ config MACH_CNS3420VB - This is a platform with an on-board ARM11 MPCore and has support - for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. - -+config MACH_GW2388 -+ bool "Support for Gateworks Laguna Platform" -+ help -+ Include support for the Gateworks Laguna Platform -+ -+ This is a platform with an on-board ARM11 MPCore and has support -+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc. -+ - endmenu ---- a/arch/arm/mach-cns3xxx/Makefile -+++ b/arch/arm/mach-cns3xxx/Makefile -@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o - cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o - cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o - cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o -+cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o -+ ---- a/arch/arm/mach-cns3xxx/devices.c -+++ b/arch/arm/mach-cns3xxx/devices.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include "cns3xxx.h" - #include "pm.h" - #include "core.h" -@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void) - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ -- gpioa_pins |= 0x1fff0004; -+ if (machine_is_gw2388()) { -+ gpioa_pins |= 0x1fff0000; -+ } else { -+ gpioa_pins |= 0x1fff0004; -+ } - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); diff --git a/target/linux/cns3xxx/patches-3.14/305-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-3.14/305-laguna_sdhci_card_detect.patch deleted file mode 100644 index 2d287851bc..0000000000 --- a/target/linux/cns3xxx/patches-3.14/305-laguna_sdhci_card_detect.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/drivers/mmc/host/sdhci-cns3xxx.c -+++ b/drivers/mmc/host/sdhci-cns3xxx.c -@@ -88,10 +88,11 @@ static const struct sdhci_pltfm_data sdh - .ops = &sdhci_cns3xxx_ops, - .quirks = SDHCI_QUIRK_BROKEN_DMA | - SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | -- SDHCI_QUIRK_INVERTED_WRITE_PROTECT | -+ //SDHCI_QUIRK_INVERTED_WRITE_PROTECT | - SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | - SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | -- SDHCI_QUIRK_NONSTANDARD_CLOCK, -+ SDHCI_QUIRK_NONSTANDARD_CLOCK | -+ SDHCI_QUIRK_BROKEN_CARD_DETECTION, - }; - - static int sdhci_cns3xxx_probe(struct platform_device *pdev) diff --git a/target/linux/cns3xxx/patches-3.14/310-pci_isolated_interrupts.patch b/target/linux/cns3xxx/patches-3.14/310-pci_isolated_interrupts.patch deleted file mode 100644 index 3e4cc67979..0000000000 --- a/target/linux/cns3xxx/patches-3.14/310-pci_isolated_interrupts.patch +++ /dev/null @@ -1,193 +0,0 @@ ---- a/arch/arm/mach-cns3xxx/cns3420vb.c -+++ b/arch/arm/mach-cns3xxx/cns3420vb.c -@@ -274,7 +274,7 @@ static int __init cns3420vb_pcie_init(vo - if (!machine_is_cns3420vb()) - return 0; - -- return cns3xxx_pcie_init(); -+ return cns3xxx_pcie_init(NULL, NULL); - } - subsys_initcall(cns3420vb_pcie_init); - ---- a/arch/arm/mach-cns3xxx/core.h -+++ b/arch/arm/mach-cns3xxx/core.h -@@ -19,7 +19,7 @@ extern void cns3xxx_pcie_iotable_init(vo - - void __init cns3xxx_map_io(void); - void __init cns3xxx_init_irq(void); --int __init cns3xxx_pcie_init(void); -+int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs); - void cns3xxx_power_off(void); - void cns3xxx_restart(enum reboot_mode, const char *); - ---- a/arch/arm/mach-cns3xxx/laguna.c -+++ b/arch/arm/mach-cns3xxx/laguna.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -868,12 +869,42 @@ static int laguna_register_gpio(struct g - return ret; - } - -+/* allow disabling of external isolated PCIe IRQs */ -+static int cns3xxx_pciextirq = 1; -+static int __init cns3xxx_pciextirq_disable(char *s) -+{ -+ cns3xxx_pciextirq = 0; -+ return 1; -+} -+__setup("noextirq", cns3xxx_pciextirq_disable); -+ - static int __init laguna_pcie_init(void) - { -+ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004); -+ u32 reg = (__raw_readl(mem) >> 26) & 0xf; -+ int irqs[] = { -+ IRQ_CNS3XXX_EXTERNAL_PIN0, -+ IRQ_CNS3XXX_EXTERNAL_PIN1, -+ IRQ_CNS3XXX_EXTERNAL_PIN2, -+ 154, -+ }; -+ - if (!machine_is_gw2388()) - return 0; - -- return cns3xxx_pcie_init(); -+ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */ -+ if (cns3xxx_pciextirq && reg != 1) -+ cns3xxx_pciextirq = 0; -+ -+ if (cns3xxx_pciextirq) { -+ printk("laguna: using isolated PCI interrupts:" -+ " irq%d/irq%d/irq%d/irq%d\n", -+ irqs[0], irqs[1], irqs[2], irqs[3]); -+ return cns3xxx_pcie_init(irqs, NULL); -+ } -+ printk("laguna: using shared PCI interrupts: irq%d\n", -+ IRQ_CNS3XXX_PCIE0_DEVICE); -+ return cns3xxx_pcie_init(NULL, NULL); - } - subsys_initcall(laguna_pcie_init); - -@@ -888,8 +919,33 @@ static int __init laguna_model_setup(voi - printk("Running on Gateworks Laguna %s\n", laguna_info.model); - cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, - NR_IRQS_CNS3XXX); -- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, -- NR_IRQS_CNS3XXX + 32); -+ -+ /* -+ * If pcie external interrupts are supported and desired -+ * configure IRQ types and configure pin function. -+ * Note that cns3xxx_pciextirq is enabled by default, but can be -+ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if -+ * the baseboard model does not support this hardware feature. -+ */ -+ if (cns3xxx_pciextirq) { -+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018); -+ reg = __raw_readl(mem); -+ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */ -+ reg &= ~0x3c000000; -+ reg |= 0x38000000; -+ __raw_writel(reg, mem); -+ -+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, -+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); -+ -+ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW); -+ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH); -+ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH); -+ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH); -+ } else { -+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, -+ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); -+ } - - if (strncmp(laguna_info.model, "GW", 2) == 0) { - if (laguna_info.config_bitmap & ETH0_LOAD) ---- a/arch/arm/mach-cns3xxx/pcie.c -+++ b/arch/arm/mach-cns3xxx/pcie.c -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - #include - #include - #include "cns3xxx.h" -@@ -32,7 +33,7 @@ enum cns3xxx_access_type { - - struct cns3xxx_pcie { - struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES]; -- unsigned int irqs[2]; -+ unsigned int irqs[6]; - struct resource res_io; - struct resource res_mem; - struct hw_pci hw_pci; -@@ -255,7 +256,7 @@ static struct pci_ops cns3xxx_pcie_ops = - static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) - { - struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); -- int irq = cnspci->irqs[slot]; -+ int irq = cnspci->irqs[slot+pin-1]; - - pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", - pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), -@@ -298,7 +299,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[ - .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, -- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, -+ .irqs = { IRQ_CNS3XXX_PCIE0_RC, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ IRQ_CNS3XXX_PCIE0_DEVICE, -+ }, - .hw_pci = { - .domain = 0, - .nr_controllers = 1, -@@ -340,7 +346,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[ - .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, -- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, -+ .irqs = { -+ IRQ_CNS3XXX_PCIE1_RC, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ IRQ_CNS3XXX_PCIE1_DEVICE, -+ }, - .hw_pci = { - .domain = 1, - .nr_controllers = 1, -@@ -460,13 +472,22 @@ void __init cns3xxx_pcie_iotable_init() - } - } - --int __init cns3xxx_pcie_init(void) -+int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs) - { - int i; - - pcibios_min_io = 0; - pcibios_min_mem = 0; - -+ if (pcie0_irqs) { -+ for (i = 0; i < 4; i++) -+ cns3xxx_pcie[0].irqs[i+1] = pcie0_irqs[i]; -+ } -+ if (pcie1_irqs) { -+ for (i = 0; i < 4; i++) -+ cns3xxx_pcie[1].irqs[i+1] = pcie1_irqs[i]; -+ } -+ - hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, - "imprecise external abort"); - diff --git a/target/linux/cns3xxx/patches-3.14/400-broadcom_phy_reinit.patch b/target/linux/cns3xxx/patches-3.14/400-broadcom_phy_reinit.patch deleted file mode 100644 index bfec081fbc..0000000000 --- a/target/linux/cns3xxx/patches-3.14/400-broadcom_phy_reinit.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/drivers/net/phy/broadcom.c -+++ b/drivers/net/phy/broadcom.c -@@ -567,6 +567,11 @@ static int bcm5481_config_aneg(struct ph - /* Write bits 14:0. */ - reg |= (1 << 15); - phy_write(phydev, 0x18, reg); -+ } else { -+ phy_write(phydev, 0x18, 0xf1e7); -+ phy_write(phydev, 0x1c, 0x8e00); -+ -+ phy_write(phydev, 0x1c, 0xa41f); - } - - return ret; -- cgit v1.2.3