From b0ae41f849c237d2e1c842a9819fb3e3ec73f9b5 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Mon, 8 Dec 2014 16:10:46 +0000 Subject: brcm63xx: add DT support for TD-W8900GB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the vendor tarball, the TD-w8900GB's flash has 64k erase block size, but CFE spans two blocks. So fixup the image offset accordingly but keep block size at its default (64k). Signed-off-by: Álvaro Fernández Rojas [jogo: add commit message, add image offset, change nvram offset] Signed-off-by: Jonas Gorski SVN-Revision: 43572 --- target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch') diff --git a/target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch b/target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch index 1d153c85a3..fd2263fe18 100644 --- a/target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch +++ b/target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch @@ -98,6 +98,6 @@ { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, #endif #ifdef CONFIG_BCM63XX_CPU_6358 - { .compatible = "alcatel,rg100a", .data = &board_96358vw2, }, -- cgit v1.2.3