From 7bcc344cf4c8437df39e3e0cdc5bacb5d0cbd9cb Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Mon, 13 Jan 2014 12:11:45 +0000 Subject: brcm63xx: update HSSPI driver with upstream submission Update the HSSPI driver with the upstream submitted one that has a workaround for the auto cs down issue. Signed-off-by: Jonas Gorski git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39264 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- ...1-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 target/linux/brcm63xx/patches-3.10/051-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch (limited to 'target/linux/brcm63xx/patches-3.10/051-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch') diff --git a/target/linux/brcm63xx/patches-3.10/051-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch b/target/linux/brcm63xx/patches-3.10/051-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch new file mode 100644 index 0000000000..6f2bc5fb50 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.10/051-MIPS-BCM63XX-setup-the-HSSPI-clock-rate.patch @@ -0,0 +1,36 @@ +From c8b7d2630d907025ce30989bddd01f4f0f13c103 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Wed, 20 Nov 2013 17:22:40 +0100 +Subject: [PATCH 2/5] MIPS: BCM63XX: setup the HSSPI clock rate + +Properly set up the HSSPI clock rate depending on the SoC's PLL rate. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/clk.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -378,3 +378,21 @@ void clk_put(struct clk *clk) + } + + EXPORT_SYMBOL(clk_put); ++ ++#define HSSPI_PLL_HZ_6328 133333333 ++#define HSSPI_PLL_HZ_6362 400000000 ++ ++static int __init bcm63xx_clk_init(void) ++{ ++ switch (bcm63xx_get_cpu_id()) { ++ case BCM6328_CPU_ID: ++ clk_hsspi.rate = HSSPI_PLL_HZ_6328; ++ break; ++ case BCM6362_CPU_ID: ++ clk_hsspi.rate = HSSPI_PLL_HZ_6362; ++ break; ++ } ++ ++ return 0; ++} ++arch_initcall(bcm63xx_clk_init); -- cgit v1.2.3