From 81573ea259247f1c6c1a7a490de174d0a6c48a64 Mon Sep 17 00:00:00 2001 From: Etienne Haarsma Date: Sat, 28 Apr 2018 21:51:24 +0200 Subject: kernel: bump kernel 4.4 to 4.4.129 for 17.01 * Refreshed patches Compile-tested: ar71xx Run-tested: ar71xx Signed-off-by: Etienne Haarsma --- ...-add-a-round-up-ability-to-the-clock-divi.patch | 6 ++--- ...cm2835-Support-for-clock-parent-selection.patch | 8 +++---- .../0254-clk-bcm2835-Add-PWM-clock-support.patch | 2 +- ...-correctly-enable-fractional-clock-suppor.patch | 6 ++--- ...-clk-bcm2835-clean-up-coding-style-issues.patch | 4 ++-- ...35-expose-raw-clock-registers-via-debugfs.patch | 14 +++++------ ...-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch | 4 ++-- ...-reorganize-bcm2835_clock_array-assignmen.patch | 4 ++-- ...lk-bcm2835-enable-management-of-PCM-clock.patch | 2 +- ...lk-bcm2835-add-missing-PLL-clock-dividers.patch | 4 ++-- ...lk-bcm2835-add-missing-osc-and-per-clocks.patch | 12 +++++----- ...lk-bcm2835-Mark-the-VPU-clock-as-critical.patch | 4 ++-- ...-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch | 4 ++-- ...-Skip-PLLC-clocks-when-deciding-on-a-new-.patch | 4 ++-- ...-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch | 6 ++--- ...-Don-t-rate-change-PLLs-on-behalf-of-divi.patch | 2 +- ...-Do-appropriate-name-lookups-for-DSI1-s-p.patch | 6 ++--- ...2835-Add-an-enum-for-the-DSI1-pixel-clock.patch | 8 +++---- ...-Clamp-the-PLL-s-requested-rate-to-the-ha.patch | 2 +- ...clk-bcm2835-Fix-fixed_divider-of-pllh_aux.patch | 2 +- ...port-rate-change-propagation-on-bcm2835-c.patch | 6 ++--- ...ow-rate-change-propagation-to-PLLH_AUX-on.patch | 2 +- ...-maybe-uninitialized-warning-in-bcm2835_c.patch | 2 +- ...-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch | 28 +++++++++++----------- 24 files changed, 71 insertions(+), 71 deletions(-) (limited to 'target/linux/brcm2708') diff --git a/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch b/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch index d9e82c78d2..8bf39adfbe 100644 --- a/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch +++ b/target/linux/brcm2708/patches-4.4/0252-clk-bcm2835-add-a-round-up-ability-to-the-clock-divi.patch @@ -16,7 +16,7 @@ Signed-off-by: Michael Turquette --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1170,22 +1170,24 @@ static int bcm2835_clock_is_on(struct cl +@@ -1172,22 +1172,24 @@ static int bcm2835_clock_is_on(struct cl static u32 bcm2835_clock_choose_div(struct clk_hw *hw, unsigned long rate, @@ -49,7 +49,7 @@ Signed-off-by: Michael Turquette /* clamp to min divider of 1 */ div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS); -@@ -1225,7 +1227,7 @@ static long bcm2835_clock_round_rate(str +@@ -1227,7 +1229,7 @@ static long bcm2835_clock_round_rate(str unsigned long *parent_rate) { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); @@ -58,7 +58,7 @@ Signed-off-by: Michael Turquette return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div); } -@@ -1294,7 +1296,7 @@ static int bcm2835_clock_set_rate(struct +@@ -1296,7 +1298,7 @@ static int bcm2835_clock_set_rate(struct struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; diff --git a/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch b/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch index afaadf6059..d436077c25 100644 --- a/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch +++ b/target/linux/brcm2708/patches-4.4/0253-clk-bcm2835-Support-for-clock-parent-selection.patch @@ -24,7 +24,7 @@ Signed-off-by: Michael Turquette --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1222,16 +1222,6 @@ static long bcm2835_clock_rate_from_divi +@@ -1224,16 +1224,6 @@ static long bcm2835_clock_rate_from_divi return temp; } @@ -41,7 +41,7 @@ Signed-off-by: Michael Turquette static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, unsigned long parent_rate) { -@@ -1303,13 +1293,75 @@ static int bcm2835_clock_set_rate(struct +@@ -1305,13 +1295,75 @@ static int bcm2835_clock_set_rate(struct return 0; } @@ -118,7 +118,7 @@ Signed-off-by: Michael Turquette }; static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) -@@ -1325,7 +1377,9 @@ static const struct clk_ops bcm2835_vpu_ +@@ -1327,7 +1379,9 @@ static const struct clk_ops bcm2835_vpu_ .is_prepared = bcm2835_vpu_clock_is_on, .recalc_rate = bcm2835_clock_get_rate, .set_rate = bcm2835_clock_set_rate, @@ -129,7 +129,7 @@ Signed-off-by: Michael Turquette }; static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, -@@ -1419,45 +1473,23 @@ static struct clk *bcm2835_register_cloc +@@ -1421,45 +1475,23 @@ static struct clk *bcm2835_register_cloc { struct bcm2835_clock *clock; struct clk_init_data init; diff --git a/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch b/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch index 8213d2b49b..65c5b6a469 100644 --- a/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch +++ b/target/linux/brcm2708/patches-4.4/0254-clk-bcm2835-Add-PWM-clock-support.patch @@ -33,7 +33,7 @@ Signed-off-by: Michael Turquette struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1607,6 +1617,9 @@ static int bcm2835_clk_probe(struct plat +@@ -1609,6 +1619,9 @@ static int bcm2835_clk_probe(struct plat cprman->regs + CM_PERIICTL, CM_GATE_BIT, 0, &cprman->regs_lock); diff --git a/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch b/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch index 33578afeff..c1f1dba4e0 100644 --- a/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch +++ b/target/linux/brcm2708/patches-4.4/0256-clk-bcm2835-correctly-enable-fractional-clock-suppor.patch @@ -66,7 +66,7 @@ Reviewed-by: Eric Anholt }; struct bcm2835_pll { -@@ -1202,7 +1206,7 @@ static u32 bcm2835_clock_choose_div(stru +@@ -1204,7 +1208,7 @@ static u32 bcm2835_clock_choose_div(stru GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; u64 rem; @@ -75,7 +75,7 @@ Reviewed-by: Eric Anholt rem = do_div(temp, rate); div = temp; -@@ -1212,11 +1216,23 @@ static u32 bcm2835_clock_choose_div(stru +@@ -1214,11 +1218,23 @@ static u32 bcm2835_clock_choose_div(stru div += unused_frac_mask + 1; div &= ~unused_frac_mask; @@ -104,7 +104,7 @@ Reviewed-by: Eric Anholt return div; } -@@ -1310,9 +1326,26 @@ static int bcm2835_clock_set_rate(struct +@@ -1312,9 +1328,26 @@ static int bcm2835_clock_set_rate(struct struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); diff --git a/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch b/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch index 62bca15035..71acdadc5e 100644 --- a/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch +++ b/target/linux/brcm2708/patches-4.4/0257-clk-bcm2835-clean-up-coding-style-issues.patch @@ -33,7 +33,7 @@ Signed-off-by: Eric Anholt const char *osc_name; struct clk_onecell_data onecell; -@@ -1350,7 +1347,7 @@ static int bcm2835_clock_set_rate(struct +@@ -1352,7 +1349,7 @@ static int bcm2835_clock_set_rate(struct } static int bcm2835_clock_determine_rate(struct clk_hw *hw, @@ -42,7 +42,7 @@ Signed-off-by: Eric Anholt { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct clk_hw *parent, *best_parent = NULL; -@@ -1408,7 +1405,6 @@ static u8 bcm2835_clock_get_parent(struc +@@ -1410,7 +1407,6 @@ static u8 bcm2835_clock_get_parent(struc return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; } diff --git a/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch b/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch index 391aab27ec..d7bcca201e 100644 --- a/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch +++ b/target/linux/brcm2708/patches-4.4/0258-clk-bcm2835-expose-raw-clock-registers-via-debugfs.patch @@ -58,7 +58,7 @@ Acked-by: Eric Anholt /* * These are fixed clocks. They're probably not all root clocks and it may * be possible to turn them on and off but until this is mapped out better -@@ -1048,6 +1070,36 @@ static int bcm2835_pll_set_rate(struct c +@@ -1050,6 +1072,36 @@ static int bcm2835_pll_set_rate(struct c return 0; } @@ -95,7 +95,7 @@ Acked-by: Eric Anholt static const struct clk_ops bcm2835_pll_clk_ops = { .is_prepared = bcm2835_pll_is_on, .prepare = bcm2835_pll_on, -@@ -1055,6 +1107,7 @@ static const struct clk_ops bcm2835_pll_ +@@ -1057,6 +1109,7 @@ static const struct clk_ops bcm2835_pll_ .recalc_rate = bcm2835_pll_get_rate, .set_rate = bcm2835_pll_set_rate, .round_rate = bcm2835_pll_round_rate, @@ -103,7 +103,7 @@ Acked-by: Eric Anholt }; struct bcm2835_pll_divider { -@@ -1157,6 +1210,26 @@ static int bcm2835_pll_divider_set_rate( +@@ -1159,6 +1212,26 @@ static int bcm2835_pll_divider_set_rate( return 0; } @@ -130,7 +130,7 @@ Acked-by: Eric Anholt static const struct clk_ops bcm2835_pll_divider_clk_ops = { .is_prepared = bcm2835_pll_divider_is_on, .prepare = bcm2835_pll_divider_on, -@@ -1164,6 +1237,7 @@ static const struct clk_ops bcm2835_pll_ +@@ -1166,6 +1239,7 @@ static const struct clk_ops bcm2835_pll_ .recalc_rate = bcm2835_pll_divider_get_rate, .set_rate = bcm2835_pll_divider_set_rate, .round_rate = bcm2835_pll_divider_round_rate, @@ -138,7 +138,7 @@ Acked-by: Eric Anholt }; /* -@@ -1405,6 +1479,31 @@ static u8 bcm2835_clock_get_parent(struc +@@ -1407,6 +1481,31 @@ static u8 bcm2835_clock_get_parent(struc return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; } @@ -170,7 +170,7 @@ Acked-by: Eric Anholt static const struct clk_ops bcm2835_clock_clk_ops = { .is_prepared = bcm2835_clock_is_on, .prepare = bcm2835_clock_on, -@@ -1414,6 +1513,7 @@ static const struct clk_ops bcm2835_cloc +@@ -1416,6 +1515,7 @@ static const struct clk_ops bcm2835_cloc .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, @@ -178,7 +178,7 @@ Acked-by: Eric Anholt }; static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) -@@ -1432,6 +1532,7 @@ static const struct clk_ops bcm2835_vpu_ +@@ -1434,6 +1534,7 @@ static const struct clk_ops bcm2835_vpu_ .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, diff --git a/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch b/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch index 17824b482b..0f2b9398ad 100644 --- a/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch +++ b/target/linux/brcm2708/patches-4.4/0259-clk-bcm2835-remove-use-of-BCM2835_CLOCK_COUNT-in-dri.patch @@ -56,7 +56,7 @@ Reviewed-by: Eric Anholt struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1664,14 +1683,81 @@ static struct clk *bcm2835_register_cloc +@@ -1666,14 +1685,81 @@ static struct clk *bcm2835_register_cloc return devm_clk_register(cprman->dev, &clock->hw); } @@ -139,7 +139,7 @@ Reviewed-by: Eric Anholt if (!cprman) return -ENOMEM; -@@ -1688,80 +1774,15 @@ static int bcm2835_clk_probe(struct plat +@@ -1690,80 +1776,15 @@ static int bcm2835_clk_probe(struct plat platform_set_drvdata(pdev, cprman); diff --git a/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch b/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch index daef89bbf6..87f2f8d113 100644 --- a/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch +++ b/target/linux/brcm2708/patches-4.4/0260-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch @@ -473,7 +473,7 @@ Reviewed-by: Eric Anholt struct bcm2835_pll { struct clk_hw hw; struct bcm2835_cprman *cprman; -@@ -1600,7 +1183,7 @@ bcm2835_register_pll_divider(struct bcm2 +@@ -1602,7 +1185,7 @@ bcm2835_register_pll_divider(struct bcm2 memset(&init, 0, sizeof(init)); @@ -482,7 +482,7 @@ Reviewed-by: Eric Anholt init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; -@@ -1699,50 +1282,401 @@ struct bcm2835_clk_desc { +@@ -1701,50 +1284,401 @@ struct bcm2835_clk_desc { const void *data; }; diff --git a/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch index a50197c20a..4adfec475b 100644 --- a/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch +++ b/target/linux/brcm2708/patches-4.4/0261-clk-bcm2835-enable-management-of-PCM-clock.patch @@ -17,7 +17,7 @@ Reviewed-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1644,6 +1644,13 @@ static const struct bcm2835_clk_desc clk +@@ -1646,6 +1646,13 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_HSMDIV, .int_bits = 4, .frac_bits = 8), diff --git a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch index d87919f9c8..683cc79cbe 100644 --- a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch +++ b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch @@ -14,7 +14,7 @@ Reviewed-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1393,6 +1393,22 @@ static const struct bcm2835_clk_desc clk +@@ -1395,6 +1395,22 @@ static const struct bcm2835_clk_desc clk .load_mask = CM_PLLA_LOADPER, .hold_mask = CM_PLLA_HOLDPER, .fixed_divider = 1), @@ -37,7 +37,7 @@ Reviewed-by: Eric Anholt /* PLLB is used for the ARM's clock. */ [BCM2835_PLLB] = REGISTER_PLL( -@@ -1507,6 +1523,22 @@ static const struct bcm2835_clk_desc clk +@@ -1509,6 +1525,22 @@ static const struct bcm2835_clk_desc clk .load_mask = CM_PLLD_LOADPER, .hold_mask = CM_PLLD_HOLDPER, .fixed_divider = 1), diff --git a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch index 9c9518e4e5..5683b04bd5 100644 --- a/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch +++ b/target/linux/brcm2708/patches-4.4/0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch @@ -26,7 +26,7 @@ Reviewed-by: Eric Anholt #define CM_EMMCCTL 0x1c0 #define CM_EMMCDIV 0x1c4 -@@ -1616,6 +1618,12 @@ static const struct bcm2835_clk_desc clk +@@ -1618,6 +1620,12 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_TSENSDIV, .int_bits = 5, .frac_bits = 0), @@ -39,7 +39,7 @@ Reviewed-by: Eric Anholt /* clocks with vpu parent mux */ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( -@@ -1630,6 +1638,7 @@ static const struct bcm2835_clk_desc clk +@@ -1632,6 +1640,7 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_ISPDIV, .int_bits = 4, .frac_bits = 8), @@ -47,7 +47,7 @@ Reviewed-by: Eric Anholt /* * Secondary SDRAM clock. Used for low-voltage modes when the PLL * in the SDRAM controller can't be used. -@@ -1661,6 +1670,36 @@ static const struct bcm2835_clk_desc clk +@@ -1663,6 +1672,36 @@ static const struct bcm2835_clk_desc clk .is_vpu_clock = true), /* clocks with per parent mux */ @@ -84,7 +84,7 @@ Reviewed-by: Eric Anholt /* Arasan EMMC clock */ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( -@@ -1669,6 +1708,29 @@ static const struct bcm2835_clk_desc clk +@@ -1671,6 +1710,29 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_EMMCDIV, .int_bits = 4, .frac_bits = 8), @@ -114,7 +114,7 @@ Reviewed-by: Eric Anholt /* HDMI state machine */ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( .name = "hsm", -@@ -1690,12 +1752,26 @@ static const struct bcm2835_clk_desc clk +@@ -1692,12 +1754,26 @@ static const struct bcm2835_clk_desc clk .int_bits = 12, .frac_bits = 12, .is_mash_clock = true), @@ -141,7 +141,7 @@ Reviewed-by: Eric Anholt /* TV encoder clock. Only operating frequency is 108Mhz. */ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( .name = "vec", -@@ -1704,6 +1780,20 @@ static const struct bcm2835_clk_desc clk +@@ -1706,6 +1782,20 @@ static const struct bcm2835_clk_desc clk .int_bits = 4, .frac_bits = 0), diff --git a/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch b/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch index 83c5accc5d..1395bebe08 100644 --- a/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch +++ b/target/linux/brcm2708/patches-4.4/0345-clk-bcm2835-Mark-the-VPU-clock-as-critical.patch @@ -27,7 +27,7 @@ Signed-off-by: Eric Anholt bool is_vpu_clock; bool is_mash_clock; }; -@@ -1248,7 +1250,7 @@ static struct clk *bcm2835_register_cloc +@@ -1250,7 +1252,7 @@ static struct clk *bcm2835_register_cloc init.parent_names = parents; init.num_parents = data->num_mux_parents; init.name = data->name; @@ -36,7 +36,7 @@ Signed-off-by: Eric Anholt if (data->is_vpu_clock) { init.ops = &bcm2835_vpu_clock_clk_ops; -@@ -1667,6 +1669,7 @@ static const struct bcm2835_clk_desc clk +@@ -1669,6 +1671,7 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_VPUDIV, .int_bits = 12, .frac_bits = 8, diff --git a/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch b/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch index 6c6a49d93a..d5d60c59a3 100644 --- a/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch +++ b/target/linux/brcm2708/patches-4.4/0346-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch @@ -19,7 +19,7 @@ Signed-off-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1252,6 +1252,15 @@ static struct clk *bcm2835_register_cloc +@@ -1254,6 +1254,15 @@ static struct clk *bcm2835_register_cloc init.name = data->name; init.flags = data->flags | CLK_IGNORE_UNUSED; @@ -35,7 +35,7 @@ Signed-off-by: Eric Anholt if (data->is_vpu_clock) { init.ops = &bcm2835_vpu_clock_clk_ops; } else { -@@ -1726,13 +1735,15 @@ static const struct bcm2835_clk_desc clk +@@ -1728,13 +1737,15 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_GP1DIV, .int_bits = 12, .frac_bits = 12, diff --git a/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch b/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch index b8e56940f5..4ba4583592 100644 --- a/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch +++ b/target/linux/brcm2708/patches-4.4/0347-clk-bcm2835-Skip-PLLC-clocks-when-deciding-on-a-new-.patch @@ -22,7 +22,7 @@ Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1026,16 +1026,28 @@ static int bcm2835_clock_set_rate(struct +@@ -1028,16 +1028,28 @@ static int bcm2835_clock_set_rate(struct return 0; } @@ -51,7 +51,7 @@ Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain /* * Select parent clock that results in the closest but lower rate */ -@@ -1043,6 +1055,17 @@ static int bcm2835_clock_determine_rate( +@@ -1045,6 +1057,17 @@ static int bcm2835_clock_determine_rate( parent = clk_hw_get_parent_by_index(hw, i); if (!parent) continue; diff --git a/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch b/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch index b456bf5f92..7eaa99f64e 100644 --- a/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch +++ b/target/linux/brcm2708/patches-4.4/0431-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch @@ -26,7 +26,7 @@ Signed-off-by: Eric Anholt #include #include #include -@@ -1845,6 +1846,25 @@ static const struct bcm2835_clk_desc clk +@@ -1847,6 +1848,25 @@ static const struct bcm2835_clk_desc clk .ctl_reg = CM_PERIICTL), }; @@ -52,7 +52,7 @@ Signed-off-by: Eric Anholt static int bcm2835_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; -@@ -1854,6 +1874,7 @@ static int bcm2835_clk_probe(struct plat +@@ -1856,6 +1876,7 @@ static int bcm2835_clk_probe(struct plat const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); size_t i; @@ -60,7 +60,7 @@ Signed-off-by: Eric Anholt cprman = devm_kzalloc(dev, sizeof(*cprman) + asize * sizeof(*clks), -@@ -1884,6 +1905,10 @@ static int bcm2835_clk_probe(struct plat +@@ -1886,6 +1907,10 @@ static int bcm2835_clk_probe(struct plat clks[i] = desc->clk_register(cprman, desc->data); } diff --git a/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch index bc92c8adc3..adc7684d71 100644 --- a/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch +++ b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch @@ -16,7 +16,7 @@ Signed-off-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1215,7 +1215,7 @@ bcm2835_register_pll_divider(struct bcm2 +@@ -1217,7 +1217,7 @@ bcm2835_register_pll_divider(struct bcm2 init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; diff --git a/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch b/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch index c357d97e61..3f3641164a 100644 --- a/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch +++ b/target/linux/brcm2708/patches-4.4/0433-clk-bcm2835-Do-appropriate-name-lookups-for-DSI1-s-p.patch @@ -64,7 +64,7 @@ Signed-off-by: Eric Anholt struct clk_onecell_data onecell; struct clk *clks[]; -@@ -1174,7 +1192,7 @@ static struct clk *bcm2835_register_pll( +@@ -1176,7 +1194,7 @@ static struct clk *bcm2835_register_pll( memset(&init, 0, sizeof(init)); /* All of the PLLs derive from the external oscillator. */ @@ -73,7 +73,7 @@ Signed-off-by: Eric Anholt init.num_parents = 1; init.name = data->name; init.ops = &bcm2835_pll_clk_ops; -@@ -1257,17 +1275,21 @@ static struct clk *bcm2835_register_cloc +@@ -1259,17 +1277,21 @@ static struct clk *bcm2835_register_cloc struct bcm2835_clock *clock; struct clk_init_data init; const char *parents[1 << CM_SRC_BITS]; @@ -102,7 +102,7 @@ Signed-off-by: Eric Anholt } memset(&init, 0, sizeof(init)); -@@ -1889,8 +1911,18 @@ static int bcm2835_clk_probe(struct plat +@@ -1891,8 +1913,18 @@ static int bcm2835_clk_probe(struct plat if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); diff --git a/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch b/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch index ad290031d7..e3a4d8c165 100644 --- a/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch +++ b/target/linux/brcm2708/patches-4.4/0434-clk-bcm2835-Add-an-enum-for-the-DSI1-pixel-clock.patch @@ -11,7 +11,7 @@ Signed-off-by: Eric Anholt --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -940,6 +940,9 @@ static long bcm2835_clock_rate_from_divi +@@ -942,6 +942,9 @@ static long bcm2835_clock_rate_from_divi const struct bcm2835_clock_data *data = clock->data; u64 temp; @@ -21,7 +21,7 @@ Signed-off-by: Eric Anholt /* * The divisor is a 12.12 fixed point field, but only some of * the bits are populated in any given clock. -@@ -963,7 +966,12 @@ static unsigned long bcm2835_clock_get_r +@@ -965,7 +968,12 @@ static unsigned long bcm2835_clock_get_r struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; @@ -35,7 +35,7 @@ Signed-off-by: Eric Anholt return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); } -@@ -1409,6 +1417,28 @@ static const char *const bcm2835_clock_v +@@ -1411,6 +1419,28 @@ static const char *const bcm2835_clock_v __VA_ARGS__) /* @@ -64,7 +64,7 @@ Signed-off-by: Eric Anholt * the real definition of all the pll, pll_dividers and clocks * these make use of the above REGISTER_* macros */ -@@ -1853,7 +1883,12 @@ static const struct bcm2835_clk_desc clk +@@ -1855,7 +1885,12 @@ static const struct bcm2835_clk_desc clk .div_reg = CM_DSI1EDIV, .int_bits = 4, .frac_bits = 8), diff --git a/target/linux/brcm2708/patches-4.4/0521-clk-bcm2835-Clamp-the-PLL-s-requested-rate-to-the-ha.patch b/target/linux/brcm2708/patches-4.4/0521-clk-bcm2835-Clamp-the-PLL-s-requested-rate-to-the-ha.patch index b209bbc523..0cc4136194 100644 --- a/target/linux/brcm2708/patches-4.4/0521-clk-bcm2835-Clamp-the-PLL-s-requested-rate-to-the-ha.patch +++ b/target/linux/brcm2708/patches-4.4/0521-clk-bcm2835-Clamp-the-PLL-s-requested-rate-to-the-ha.patch @@ -27,7 +27,7 @@ Signed-off-by: Eric Anholt bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); -@@ -631,13 +635,6 @@ static int bcm2835_pll_set_rate(struct c +@@ -633,13 +637,6 @@ static int bcm2835_pll_set_rate(struct c u32 ana[4]; int i; diff --git a/target/linux/brcm2708/patches-4.4/0580-clk-bcm2835-Fix-fixed_divider-of-pllh_aux.patch b/target/linux/brcm2708/patches-4.4/0580-clk-bcm2835-Fix-fixed_divider-of-pllh_aux.patch index 72f3ec6515..7b8f55880c 100644 --- a/target/linux/brcm2708/patches-4.4/0580-clk-bcm2835-Fix-fixed_divider-of-pllh_aux.patch +++ b/target/linux/brcm2708/patches-4.4/0580-clk-bcm2835-Fix-fixed_divider-of-pllh_aux.patch @@ -16,7 +16,7 @@ Signed-off-by: Stephen Boyd --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1661,7 +1661,7 @@ static const struct bcm2835_clk_desc clk +@@ -1663,7 +1663,7 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLH_AUX, .load_mask = CM_PLLH_LOADAUX, .hold_mask = 0, diff --git a/target/linux/brcm2708/patches-4.4/0581-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch b/target/linux/brcm2708/patches-4.4/0581-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch index fab8fe7164..d04059cd02 100644 --- a/target/linux/brcm2708/patches-4.4/0581-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch +++ b/target/linux/brcm2708/patches-4.4/0581-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch @@ -34,7 +34,7 @@ Signed-off-by: Stephen Boyd u32 ctl_reg; u32 div_reg; -@@ -1059,10 +1062,60 @@ bcm2835_clk_is_pllc(struct clk_hw *hw) +@@ -1061,10 +1064,60 @@ bcm2835_clk_is_pllc(struct clk_hw *hw) return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; } @@ -96,7 +96,7 @@ Signed-off-by: Stephen Boyd struct clk_hw *parent, *best_parent = NULL; bool current_parent_is_pllc; unsigned long rate, best_rate = 0; -@@ -1090,9 +1143,8 @@ static int bcm2835_clock_determine_rate( +@@ -1092,9 +1145,8 @@ static int bcm2835_clock_determine_rate( if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) continue; @@ -108,7 +108,7 @@ Signed-off-by: Stephen Boyd if (rate > best_rate && rate <= req->rate) { best_parent = parent; best_prate = prate; -@@ -1312,6 +1364,13 @@ static struct clk *bcm2835_register_cloc +@@ -1314,6 +1366,13 @@ static struct clk *bcm2835_register_cloc if ((cprman_read(cprman, data->ctl_reg) & CM_ENABLE) == 0) init.flags &= ~CLK_IS_CRITICAL; diff --git a/target/linux/brcm2708/patches-4.4/0582-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch b/target/linux/brcm2708/patches-4.4/0582-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch index 9bf5ea3033..5d403b2a03 100644 --- a/target/linux/brcm2708/patches-4.4/0582-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch +++ b/target/linux/brcm2708/patches-4.4/0582-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch @@ -19,7 +19,7 @@ Signed-off-by: Stephen Boyd --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1924,7 +1924,12 @@ static const struct bcm2835_clk_desc clk +@@ -1926,7 +1926,12 @@ static const struct bcm2835_clk_desc clk .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, .int_bits = 4, diff --git a/target/linux/brcm2708/patches-4.4/0583-clk-bcm-Fix-maybe-uninitialized-warning-in-bcm2835_c.patch b/target/linux/brcm2708/patches-4.4/0583-clk-bcm-Fix-maybe-uninitialized-warning-in-bcm2835_c.patch index e8e4d24ceb..bc86027eba 100644 --- a/target/linux/brcm2708/patches-4.4/0583-clk-bcm-Fix-maybe-uninitialized-warning-in-bcm2835_c.patch +++ b/target/linux/brcm2708/patches-4.4/0583-clk-bcm-Fix-maybe-uninitialized-warning-in-bcm2835_c.patch @@ -18,7 +18,7 @@ Signed-off-by: Stephen Boyd --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1071,7 +1071,7 @@ static unsigned long bcm2835_clock_choos +@@ -1073,7 +1073,7 @@ static unsigned long bcm2835_clock_choos struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; diff --git a/target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch b/target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch index d91bb5672e..c79ffb5e8e 100644 --- a/target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch +++ b/target/linux/brcm2708/patches-4.4/0584-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch @@ -31,7 +31,7 @@ Signed-off-by: Stephen Boyd }; struct bcm2835_clock_data { -@@ -1290,7 +1291,7 @@ bcm2835_register_pll_divider(struct bcm2 +@@ -1292,7 +1293,7 @@ bcm2835_register_pll_divider(struct bcm2 init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; @@ -40,7 +40,7 @@ Signed-off-by: Stephen Boyd divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); if (!divider) -@@ -1529,7 +1530,8 @@ static const struct bcm2835_clk_desc clk +@@ -1531,7 +1532,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLA_CORE, .load_mask = CM_PLLA_LOADCORE, .hold_mask = CM_PLLA_HOLDCORE, @@ -50,7 +50,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( .name = "plla_per", .source_pll = "plla", -@@ -1537,7 +1539,8 @@ static const struct bcm2835_clk_desc clk +@@ -1539,7 +1541,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLA_PER, .load_mask = CM_PLLA_LOADPER, .hold_mask = CM_PLLA_HOLDPER, @@ -60,7 +60,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( .name = "plla_dsi0", .source_pll = "plla", -@@ -1553,7 +1556,8 @@ static const struct bcm2835_clk_desc clk +@@ -1555,7 +1558,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLA_CCP2, .load_mask = CM_PLLA_LOADCCP2, .hold_mask = CM_PLLA_HOLDCCP2, @@ -70,7 +70,7 @@ Signed-off-by: Stephen Boyd /* PLLB is used for the ARM's clock. */ [BCM2835_PLLB] = REGISTER_PLL( -@@ -1577,7 +1581,8 @@ static const struct bcm2835_clk_desc clk +@@ -1579,7 +1583,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLB_ARM, .load_mask = CM_PLLB_LOADARM, .hold_mask = CM_PLLB_HOLDARM, @@ -80,7 +80,7 @@ Signed-off-by: Stephen Boyd /* * PLLC is the core PLL, used to drive the core VPU clock. -@@ -1606,7 +1611,8 @@ static const struct bcm2835_clk_desc clk +@@ -1608,7 +1613,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_CORE0, .load_mask = CM_PLLC_LOADCORE0, .hold_mask = CM_PLLC_HOLDCORE0, @@ -90,7 +90,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( .name = "pllc_core1", .source_pll = "pllc", -@@ -1614,7 +1620,8 @@ static const struct bcm2835_clk_desc clk +@@ -1616,7 +1622,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_CORE1, .load_mask = CM_PLLC_LOADCORE1, .hold_mask = CM_PLLC_HOLDCORE1, @@ -100,7 +100,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( .name = "pllc_core2", .source_pll = "pllc", -@@ -1622,7 +1629,8 @@ static const struct bcm2835_clk_desc clk +@@ -1624,7 +1631,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_CORE2, .load_mask = CM_PLLC_LOADCORE2, .hold_mask = CM_PLLC_HOLDCORE2, @@ -110,7 +110,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( .name = "pllc_per", .source_pll = "pllc", -@@ -1630,7 +1638,8 @@ static const struct bcm2835_clk_desc clk +@@ -1632,7 +1640,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_PER, .load_mask = CM_PLLC_LOADPER, .hold_mask = CM_PLLC_HOLDPER, @@ -120,7 +120,7 @@ Signed-off-by: Stephen Boyd /* * PLLD is the display PLL, used to drive DSI display panels. -@@ -1659,7 +1668,8 @@ static const struct bcm2835_clk_desc clk +@@ -1661,7 +1670,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLD_CORE, .load_mask = CM_PLLD_LOADCORE, .hold_mask = CM_PLLD_HOLDCORE, @@ -130,7 +130,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( .name = "plld_per", .source_pll = "plld", -@@ -1667,7 +1677,8 @@ static const struct bcm2835_clk_desc clk +@@ -1669,7 +1679,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLD_PER, .load_mask = CM_PLLD_LOADPER, .hold_mask = CM_PLLD_HOLDPER, @@ -140,7 +140,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( .name = "plld_dsi0", .source_pll = "plld", -@@ -1712,7 +1723,8 @@ static const struct bcm2835_clk_desc clk +@@ -1714,7 +1725,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLH_RCAL, .load_mask = CM_PLLH_LOADRCAL, .hold_mask = 0, @@ -150,7 +150,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( .name = "pllh_aux", .source_pll = "pllh", -@@ -1720,7 +1732,8 @@ static const struct bcm2835_clk_desc clk +@@ -1722,7 +1734,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLH_AUX, .load_mask = CM_PLLH_LOADAUX, .hold_mask = 0, @@ -160,7 +160,7 @@ Signed-off-by: Stephen Boyd [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( .name = "pllh_pix", .source_pll = "pllh", -@@ -1728,7 +1741,8 @@ static const struct bcm2835_clk_desc clk +@@ -1730,7 +1743,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLH_PIX, .load_mask = CM_PLLH_LOADPIX, .hold_mask = 0, -- cgit v1.2.3