From c30f7f402f1be7a7917b3dd604ee32be8ed20716 Mon Sep 17 00:00:00 2001 From: Stijn Tintel Date: Sat, 2 Feb 2019 21:53:15 +0100 Subject: brcm2708: drop 4.9 support Signed-off-by: Stijn Tintel --- ...ow-rate-change-propagation-to-PLLH_AUX-on.patch | 35 ---------------------- 1 file changed, 35 deletions(-) delete mode 100644 target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch (limited to 'target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch') diff --git a/target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch b/target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch deleted file mode 100644 index bab7161428..0000000000 --- a/target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5209e1b8f78fd1184f25cf19cf0daa58f4ad6599 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Thu, 1 Dec 2016 22:00:20 +0100 -Subject: [PATCH] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC - clock - -The VEC clock requires needs to be set at exactly 108MHz. Allow rate -change propagation on PLLH_AUX to match this requirement wihtout -impacting other IPs (PLLH is currently only used by the HDMI encoder, -which cannot be enabled when the VEC encoder is enabled). - -Signed-off-by: Boris Brezillon -Reviewed-by: Eric Anholt -Signed-off-by: Stephen Boyd -(cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd) ---- - drivers/clk/bcm/clk-bcm2835.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/clk/bcm/clk-bcm2835.c -+++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -1876,7 +1876,12 @@ static const struct bcm2835_clk_desc clk - .ctl_reg = CM_VECCTL, - .div_reg = CM_VECDIV, - .int_bits = 4, -- .frac_bits = 0), -+ .frac_bits = 0, -+ /* -+ * Allow rate change propagation only on PLLH_AUX which is -+ * assigned index 7 in the parent array. -+ */ -+ .set_rate_parent = BIT(7)), - - /* dsi clocks */ - [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( -- cgit v1.2.3