From dab5a4406799633a319381b0127e1fda82b15c02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Mon, 6 Feb 2017 17:12:09 +0100 Subject: brcm2708: update linux 4.4 patches to latest version n As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas --- ...ow-rate-change-propagation-to-PLLH_AUX-on.patch | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 target/linux/brcm2708/patches-4.4/0581-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch (limited to 'target/linux/brcm2708/patches-4.4/0581-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch') diff --git a/target/linux/brcm2708/patches-4.4/0581-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch b/target/linux/brcm2708/patches-4.4/0581-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch new file mode 100644 index 0000000000..4b22762566 --- /dev/null +++ b/target/linux/brcm2708/patches-4.4/0581-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch @@ -0,0 +1,35 @@ +From e7a3b8bd6756b59696a430a0c83e3e609915dea6 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Thu, 1 Dec 2016 22:00:20 +0100 +Subject: [PATCH] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC + clock + +The VEC clock requires needs to be set at exactly 108MHz. Allow rate +change propagation on PLLH_AUX to match this requirement wihtout +impacting other IPs (PLLH is currently only used by the HDMI encoder, +which cannot be enabled when the VEC encoder is enabled). + +Signed-off-by: Boris Brezillon +Reviewed-by: Eric Anholt +Signed-off-by: Stephen Boyd +(cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd) +--- + drivers/clk/bcm/clk-bcm2835.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -1920,7 +1920,12 @@ static const struct bcm2835_clk_desc clk + .ctl_reg = CM_VECCTL, + .div_reg = CM_VECDIV, + .int_bits = 4, +- .frac_bits = 0), ++ .frac_bits = 0, ++ /* ++ * Allow rate change propagation only on PLLH_AUX which is ++ * assigned index 7 in the parent array. ++ */ ++ .set_rate_parent = BIT(7)), + + /* dsi clocks */ + [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( -- cgit v1.2.3