From 2b1c6b21b5e6c82ebb55d7fb7df90e60e88cbb14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sat, 10 Sep 2016 14:54:26 +0200 Subject: brcm2708: update linux 4.4 patches to latest version MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Also adds support for Raspberry Pi Compute Module 3 (untested). Signed-off-by: Álvaro Fernández Rojas --- ...-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch (limited to 'target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch') diff --git a/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch new file mode 100644 index 0000000000..a24afc8632 --- /dev/null +++ b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Mark-the-CM-SDRAM-clock-s-parent-as-crit.patch @@ -0,0 +1,73 @@ +From a916fdb4aef02300a69cb49fb20f36ab4dc91673 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Wed, 1 Jun 2016 12:05:35 -0700 +Subject: [PATCH] clk: bcm2835: Mark the CM SDRAM clock's parent as critical + +While the SDRAM is being driven by its dedicated PLL most of the time, +there is a little loop running in the firmware that periodically turns +on the CM SDRAM clock (using its pre-initialized parent) and switches +SDRAM to using the CM clock to do PVT recalibration. + +This avoids system hangs if we choose SDRAM's parent for some other +clock, then disable that clock. + +Signed-off-by: Eric Anholt +--- + drivers/clk/bcm/clk-bcm2835.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -36,6 +36,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -1839,6 +1840,25 @@ static const struct bcm2835_clk_desc clk + .ctl_reg = CM_PERIICTL), + }; + ++/* ++ * Permanently take a reference on the parent of the SDRAM clock. ++ * ++ * While the SDRAM is being driven by its dedicated PLL most of the ++ * time, there is a little loop running in the firmware that ++ * periodically switches the SDRAM to using our CM clock to do PVT ++ * recalibration, with the assumption that the previously configured ++ * SDRAM parent is still enabled and running. ++ */ ++static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) ++{ ++ struct clk *parent = clk_get_parent(sdc); ++ ++ if (IS_ERR(parent)) ++ return PTR_ERR(parent); ++ ++ return clk_prepare_enable(parent); ++} ++ + static int bcm2835_clk_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +@@ -1848,6 +1868,7 @@ static int bcm2835_clk_probe(struct plat + const struct bcm2835_clk_desc *desc; + const size_t asize = ARRAY_SIZE(clk_desc_array); + size_t i; ++ int ret; + + cprman = devm_kzalloc(dev, + sizeof(*cprman) + asize * sizeof(*clks), +@@ -1878,6 +1899,10 @@ static int bcm2835_clk_probe(struct plat + clks[i] = desc->clk_register(cprman, desc->data); + } + ++ ret = bcm2835_mark_sdc_parent_critical(clks[BCM2835_CLOCK_SDRAM]); ++ if (ret) ++ return ret; ++ + return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, + &cprman->onecell); + } -- cgit v1.2.3