From 20402106a376dcc4a766d3b0cee801ce29ba76d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 7 Jul 2016 09:22:07 +0200 Subject: brcm2708: update linux 4.4 patches to latest version MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas --- ...lk-bcm2835-add-missing-PLL-clock-dividers.patch | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch (limited to 'target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch') diff --git a/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch new file mode 100644 index 0000000000..dd71a4d6e7 --- /dev/null +++ b/target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-add-missing-PLL-clock-dividers.patch @@ -0,0 +1,73 @@ +From bea282aec8f05b08fd5185f7aeb75050a00c1d49 Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Mon, 29 Feb 2016 15:43:56 +0000 +Subject: [PATCH 262/423] clk: bcm2835: add missing PLL clock dividers + +Signed-off-by: Martin Sperl +Signed-off-by: Eric Anholt +Reviewed-by: Eric Anholt +(cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32) +--- + drivers/clk/bcm/clk-bcm2835.c | 32 ++++++++++++++++++++++++++++++++ + include/dt-bindings/clock/bcm2835.h | 5 +++++ + 2 files changed, 37 insertions(+) + +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -1387,6 +1387,22 @@ static const struct bcm2835_clk_desc clk + .load_mask = CM_PLLA_LOADPER, + .hold_mask = CM_PLLA_HOLDPER, + .fixed_divider = 1), ++ [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( ++ .name = "plla_dsi0", ++ .source_pll = "plla", ++ .cm_reg = CM_PLLA, ++ .a2w_reg = A2W_PLLA_DSI0, ++ .load_mask = CM_PLLA_LOADDSI0, ++ .hold_mask = CM_PLLA_HOLDDSI0, ++ .fixed_divider = 1), ++ [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( ++ .name = "plla_ccp2", ++ .source_pll = "plla", ++ .cm_reg = CM_PLLA, ++ .a2w_reg = A2W_PLLA_CCP2, ++ .load_mask = CM_PLLA_LOADCCP2, ++ .hold_mask = CM_PLLA_HOLDCCP2, ++ .fixed_divider = 1), + + /* PLLB is used for the ARM's clock. */ + [BCM2835_PLLB] = REGISTER_PLL( +@@ -1501,6 +1517,22 @@ static const struct bcm2835_clk_desc clk + .load_mask = CM_PLLD_LOADPER, + .hold_mask = CM_PLLD_HOLDPER, + .fixed_divider = 1), ++ [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( ++ .name = "plld_dsi0", ++ .source_pll = "plld", ++ .cm_reg = CM_PLLD, ++ .a2w_reg = A2W_PLLD_DSI0, ++ .load_mask = CM_PLLD_LOADDSI0, ++ .hold_mask = CM_PLLD_HOLDDSI0, ++ .fixed_divider = 1), ++ [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( ++ .name = "plld_dsi1", ++ .source_pll = "plld", ++ .cm_reg = CM_PLLD, ++ .a2w_reg = A2W_PLLD_DSI1, ++ .load_mask = CM_PLLD_LOADDSI1, ++ .hold_mask = CM_PLLD_HOLDDSI1, ++ .fixed_divider = 1), + + /* + * PLLH is used to supply the pixel clock or the AUX clock for the +--- a/include/dt-bindings/clock/bcm2835.h ++++ b/include/dt-bindings/clock/bcm2835.h +@@ -45,3 +45,8 @@ + #define BCM2835_CLOCK_PERI_IMAGE 29 + #define BCM2835_CLOCK_PWM 30 + #define BCM2835_CLOCK_PCM 31 ++ ++#define BCM2835_PLLA_DSI0 32 ++#define BCM2835_PLLA_CCP2 33 ++#define BCM2835_PLLD_DSI0 34 ++#define BCM2835_PLLD_DSI1 35 -- cgit v1.2.3