From d78864ef7c7b550de88f8494fed22bf6854c6627 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@openwrt.org>
Date: Thu, 14 Dec 2006 16:41:33 +0000
Subject: Upgrade to Linux 2.6.19

- Includes large parts of the patch from #1021 by dpalffy
- Includes RB532 NAND driver changes by n0-1



git-svn-id: svn://svn.openwrt.org/openwrt/trunk@5789 3c298f89-4303-0410-b956-a3cf2f4a3e73
---
 .../linux/brcm-2.6/patches/005-remove_scache.patch | 94 ++++++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 target/linux/brcm-2.6/patches/005-remove_scache.patch

(limited to 'target/linux/brcm-2.6/patches/005-remove_scache.patch')

diff --git a/target/linux/brcm-2.6/patches/005-remove_scache.patch b/target/linux/brcm-2.6/patches/005-remove_scache.patch
new file mode 100644
index 0000000000..f56f72f176
--- /dev/null
+++ b/target/linux/brcm-2.6/patches/005-remove_scache.patch
@@ -0,0 +1,94 @@
+diff -urN linux-2.6.19.ref/arch/mips/Kconfig linux-2.6.19/arch/mips/Kconfig
+--- linux-2.6.19.ref/arch/mips/Kconfig	2006-12-04 21:33:48.000000000 +0100
++++ linux-2.6.19/arch/mips/Kconfig	2006-12-04 21:34:04.000000000 +0100
+@@ -283,7 +283,6 @@
+ 	select I8259
+ 	select MIPS_BOARDS_GEN
+ 	select MIPS_BONITO64
+-	select MIPS_CPU_SCACHE
+ 	select MIPS_GT64120
+ 	select MIPS_MSC
+ 	select SWAP_IO_SPACE
+@@ -1434,13 +1433,6 @@
+ 	bool
+ 	select BOARD_SCACHE
+ 
+-#
+-# Support for a MIPS32 / MIPS64 style S-caches
+-#
+-config MIPS_CPU_SCACHE
+-	bool
+-	select BOARD_SCACHE
+-
+ config R5000_CPU_SCACHE
+ 	bool
+ 	select BOARD_SCACHE
+diff -urN linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c linux-2.6.19/arch/mips/kernel/cpu-probe.c
+--- linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c	2006-12-04 21:33:48.000000000 +0100
++++ linux-2.6.19/arch/mips/kernel/cpu-probe.c	2006-12-04 21:34:04.000000000 +0100
+@@ -631,6 +631,8 @@
+ 		break;
+ 	case PRID_IMP_25KF:
+ 		c->cputype = CPU_25KF;
++		/* Probe for L2 cache */
++		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+ 		break;
+ 	case PRID_IMP_34K:
+ 		c->cputype = CPU_34K;
+diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
+--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c	2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/arch/mips/mm/c-r4k.c	2006-12-04 21:34:04.000000000 +0100
+@@ -1038,7 +1038,6 @@
+ 
+ extern int r5k_sc_init(void);
+ extern int rm7k_sc_init(void);
+-extern int mips_sc_init(void);
+ 
+ static void __init setup_scache(void)
+ {
+@@ -1086,29 +1085,17 @@
+ 		return;
+ 
+ 	default:
+-		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+-		    c->isa_level == MIPS_CPU_ISA_M32R2 ||
+-		    c->isa_level == MIPS_CPU_ISA_M64R1 ||
+-		    c->isa_level == MIPS_CPU_ISA_M64R2) {
+-#ifdef CONFIG_MIPS_CPU_SCACHE
+-			if (mips_sc_init ()) {
+-				scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+-				printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+-				       scache_size >> 10,
+-				       way_string[c->scache.ways], c->scache.linesz);
+-			}
+-#else
+-			if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+-				panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+-#endif
+-			return;
+-		}
+ 		sc_present = 0;
+ 	}
+ 
+ 	if (!sc_present)
+ 		return;
+ 
++	if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
++	     c->isa_level == MIPS_CPU_ISA_M64R1) &&
++	    !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
++		panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
++
+ 	/* compute a couple of other cache variables */
+ 	c->scache.waysize = scache_size / c->scache.ways;
+ 
+diff -urN linux-2.6.19.ref/arch/mips/mm/Makefile linux-2.6.19/arch/mips/mm/Makefile
+--- linux-2.6.19.ref/arch/mips/mm/Makefile	2006-11-29 22:57:37.000000000 +0100
++++ linux-2.6.19/arch/mips/mm/Makefile	2006-12-04 21:34:04.000000000 +0100
+@@ -30,7 +30,6 @@
+ obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
+ obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
+ obj-$(CONFIG_RM7000_CPU_SCACHE)	+= sc-rm7k.o
+-obj-$(CONFIG_MIPS_CPU_SCACHE)	+= sc-mips.o
+ 
+ #
+ # Choose one DMA coherency model
-- 
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