From 77e97abf129c5028385dd72587eabab68db0d954 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 28 May 2020 19:08:55 +0200 Subject: bcm27xx: update to latest patches from RPi foundation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also removes random module and switches to new bcm2711 thermal driver. Boot tested on RPi 4B v1.1 4G. Signed-off-by: Álvaro Fernández Rojas --- ...c-Add-function-to-compute-FIFO-level-bits.patch | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 target/linux/bcm27xx/patches-5.4/950-0563-drm-vc4-crtc-Add-function-to-compute-FIFO-level-bits.patch (limited to 'target/linux/bcm27xx/patches-5.4/950-0563-drm-vc4-crtc-Add-function-to-compute-FIFO-level-bits.patch') diff --git a/target/linux/bcm27xx/patches-5.4/950-0563-drm-vc4-crtc-Add-function-to-compute-FIFO-level-bits.patch b/target/linux/bcm27xx/patches-5.4/950-0563-drm-vc4-crtc-Add-function-to-compute-FIFO-level-bits.patch new file mode 100644 index 0000000000..77952c0eea --- /dev/null +++ b/target/linux/bcm27xx/patches-5.4/950-0563-drm-vc4-crtc-Add-function-to-compute-FIFO-level-bits.patch @@ -0,0 +1,44 @@ +From 2c241c25b76d105f798881e1a3c6e3c09c3b27ff Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 13 Jan 2020 13:40:37 +0100 +Subject: [PATCH] drm/vc4: crtc: Add function to compute FIFO level + bits + +The longer FIFOs in vc5 pixelvalves means that the FIFO full level +doesn't fit in the original register field and that we also have a +secondary field. In order to prepare for this, let's move the registers +fill part to a helper function. + +Signed-off-by: Maxime Ripard +--- + drivers/gpu/drm/vc4/vc4_crtc.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/vc4/vc4_crtc.c ++++ b/drivers/gpu/drm/vc4/vc4_crtc.c +@@ -277,6 +277,14 @@ static u32 vc4_get_fifo_full_level(struc + } + } + ++static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, ++ u32 format) ++{ ++ u32 level = vc4_get_fifo_full_level(vc4_crtc, format); ++ return VC4_SET_FIELD(level & 0x3f, ++ PV_CONTROL_FIFO_LEVEL); ++} ++ + /* + * Returns the encoder attached to the CRTC. + * +@@ -377,9 +385,8 @@ static void vc4_crtc_config_pv(struct dr + CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); + + CRTC_WRITE(PV_CONTROL, ++ vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | + VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | +- VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format), +- PV_CONTROL_FIFO_LEVEL) | + VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | + PV_CONTROL_CLR_AT_START | + PV_CONTROL_TRIGGER_UNDERFLOW | -- cgit v1.2.3