From f07e572f6447465d8938679533d604e402b0f066 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 18 Feb 2021 18:04:33 +0100 Subject: bcm27xx: import latest patches from the RPi foundation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G bcm2710: boot tested on RPi 3B v1.2 bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas --- ...media-tc358743-Increase-FIFO-level-to-374.patch | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 target/linux/bcm27xx/patches-5.4/950-0152-media-tc358743-Increase-FIFO-level-to-374.patch (limited to 'target/linux/bcm27xx/patches-5.4/950-0152-media-tc358743-Increase-FIFO-level-to-374.patch') diff --git a/target/linux/bcm27xx/patches-5.4/950-0152-media-tc358743-Increase-FIFO-level-to-374.patch b/target/linux/bcm27xx/patches-5.4/950-0152-media-tc358743-Increase-FIFO-level-to-374.patch new file mode 100644 index 0000000000..8ec643f102 --- /dev/null +++ b/target/linux/bcm27xx/patches-5.4/950-0152-media-tc358743-Increase-FIFO-level-to-374.patch @@ -0,0 +1,31 @@ +From e9d49d1b54bb1f202ac8d4a42c5ebb9a9237da17 Mon Sep 17 00:00:00 2001 +From: Dave Stevenson +Date: Wed, 31 Oct 2018 14:56:59 +0000 +Subject: [PATCH] media: tc358743: Increase FIFO level to 374. + +The existing fixed value of 16 worked for UYVY 720P60 over +2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888 +1080P60 needs 6 lanes at 594MHz). +It doesn't allow for lower resolutions to work as the FIFO +underflows. + +374 is required for 1080P24-30 UYVY over 2 lanes @ 972Mbit/s, but +>374 means that the FIFO underflows on 1080P50 UYVY over 2 lanes +@ 972Mbit/s. + +Signed-off-by: Dave Stevenson +--- + drivers/media/i2c/tc358743.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/media/i2c/tc358743.c ++++ b/drivers/media/i2c/tc358743.c +@@ -1949,7 +1949,7 @@ static int tc358743_probe_of(struct tc35 + state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; + state->pdata.enable_hdcp = false; + /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ +- state->pdata.fifo_level = 16; ++ state->pdata.fifo_level = 374; + /* + * The PLL input clock is obtained by dividing refclk by pll_prd. + * It must be between 6 MHz and 40 MHz, lower frequency is better. -- cgit v1.2.3