From c13d383c2be23f646e0de054eb8ea7d4bce115f6 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Thu, 15 Feb 2007 21:52:13 +0000 Subject: some ar531x cleanup SVN-Revision: 6302 --- .../atheros-2.6/files/arch/mips/atheros/ar5312.c | 24 +++++------- .../atheros-2.6/files/arch/mips/atheros/ar5312.h | 11 ++++++ .../atheros-2.6/files/arch/mips/atheros/ar5315.c | 16 +++----- .../atheros-2.6/files/arch/mips/atheros/ar5315.h | 44 +++++++++++++--------- 4 files changed, 52 insertions(+), 43 deletions(-) (limited to 'target/linux/atheros-2.6/files/arch/mips') diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c index 28b9d3f958..4e1beaae38 100644 --- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c +++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c @@ -30,12 +30,6 @@ #include "ar531x.h" -#define AR531X_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -#define AR531X_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -#define AR531X_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -#define AR531X_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -#define AR531X_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ - static struct platform_device *ar5312_devs[5]; @@ -49,8 +43,8 @@ static struct resource ar5312_eth0_res[] = { { .name = "eth_irq", .flags = IORESOURCE_IRQ, - .start = AR531X_IRQ_ENET0_INTRS, - .end = AR531X_IRQ_ENET0_INTRS, + .start = AR5312_IRQ_ENET0_INTRS, + .end = AR5312_IRQ_ENET0_INTRS, }, }; @@ -65,8 +59,8 @@ static struct resource ar5312_eth1_res[] = { { .name = "eth_irq", .flags = IORESOURCE_IRQ, - .start = AR531X_IRQ_ENET1_INTRS, - .end = AR531X_IRQ_ENET1_INTRS, + .start = AR5312_IRQ_ENET1_INTRS, + .end = AR5312_IRQ_ENET1_INTRS, }, }; @@ -221,13 +215,13 @@ asmlinkage void ar5312_irq_dispatch(void) int pending = read_c0_status() & read_c0_cause(); if (pending & CAUSEF_IP2) - do_IRQ(AR531X_IRQ_WLAN0_INTRS); + do_IRQ(AR5312_IRQ_WLAN0_INTRS); else if (pending & CAUSEF_IP3) - do_IRQ(AR531X_IRQ_ENET0_INTRS); + do_IRQ(AR5312_IRQ_ENET0_INTRS); else if (pending & CAUSEF_IP4) - do_IRQ(AR531X_IRQ_ENET1_INTRS); + do_IRQ(AR5312_IRQ_ENET1_INTRS); else if (pending & CAUSEF_IP5) - do_IRQ(AR531X_IRQ_WLAN1_INTRS); + do_IRQ(AR5312_IRQ_WLAN1_INTRS); else if (pending & CAUSEF_IP6) { unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR); @@ -448,7 +442,7 @@ void __init ar5312_misc_intr_init(int irq_base) irq_desc[i].chip = &ar5312_misc_intr_controller; } setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); - setup_irq(AR531X_IRQ_MISC_INTRS, &cascade); + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); } diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.h b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.h index b6e71b8901..62d5797933 100644 --- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.h +++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.h @@ -13,6 +13,17 @@ #include +/* + * IRQs + */ + +#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ +#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ +#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ +#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ +#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ + + /* Address Map */ #define AR531X_WLAN0 0x18000000 #define AR531X_WLAN1 0x18500000 diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.c b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.c index 78b2835914..b0db7c1d02 100644 --- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.c +++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.c @@ -28,12 +28,6 @@ #include #include "ar531x.h" -#define AR531X_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -#define AR531X_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -#define AR531X_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -#define AR531X_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -#define AR531X_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ - static struct resource ar5315_eth_res[] = { { .name = "eth_membase", @@ -44,8 +38,8 @@ static struct resource ar5315_eth_res[] = { { .name = "eth_irq", .flags = IORESOURCE_IRQ, - .start = AR531X_IRQ_ENET0_INTRS, - .end = AR531X_IRQ_ENET0_INTRS, + .start = AR5315_IRQ_ENET0_INTRS, + .end = AR5315_IRQ_ENET0_INTRS, }, }; @@ -218,9 +212,9 @@ asmlinkage void ar5315_irq_dispatch(void) int pending = read_c0_status() & read_c0_cause(); if (pending & CAUSEF_IP3) - do_IRQ(AR531X_IRQ_WLAN0_INTRS); + do_IRQ(AR5315_IRQ_WLAN0_INTRS); else if (pending & CAUSEF_IP4) - do_IRQ(AR531X_IRQ_ENET0_INTRS); + do_IRQ(AR5315_IRQ_ENET0_INTRS); else if (pending & CAUSEF_IP2) { unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR); @@ -504,7 +498,7 @@ void ar5315_misc_intr_init(int irq_base) irq_desc[i].chip = &ar5315_misc_intr_controller; } setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt); - setup_irq(AR531X_IRQ_MISC_INTRS, &cascade); + setup_irq(AR5315_IRQ_MISC_INTRS, &cascade); } void __init ar5315_plat_setup(void) diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h index b523f80405..ef2df8778d 100644 --- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h +++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h @@ -12,6 +12,16 @@ #ifndef AR5315_H #define AR5315_H +/* + * IRQs + */ +#define AR5315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ +#define AR5315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ +#define AR5315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ +#define AR5315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ +#define AR5315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ + + /* * Address map */ @@ -80,23 +90,23 @@ */ #define AR5315_ENDIAN_CTL (AR5315_DSLBASE + 0x000c) -#define CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ -#define CONFIG_WLAN 0x00000002 /* WLAN byteswap */ -#define CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ -#define CONFIG_PCI 0x00000008 /* PCI byteswap */ -#define CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ -#define CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ -#define CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ - -#define CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ -#define CONFIG_CPU 0x00000400 /* CPU big endian */ -#define CONFIG_PCIAHB 0x00000800 -#define CONFIG_PCIAHB_BRIDGE 0x00001000 -#define CONFIG_SPI 0x00008000 /* SPI byteswap */ -#define CONFIG_CPU_DRAM 0x00010000 -#define CONFIG_CPU_PCI 0x00020000 -#define CONFIG_CPU_MMR 0x00040000 -#define CONFIG_BIG 0x00000400 +#define AR5315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ +#define AR5315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ +#define AR5315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ +#define AR5315_CONFIG_PCI 0x00000008 /* PCI byteswap */ +#define AR5315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ +#define AR5315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ +#define AR5315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ + +#define AR5315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ +#define AR5315_CONFIG_CPU 0x00000400 /* CPU big endian */ +#define AR5315_CONFIG_PCIAHB 0x00000800 +#define AR5315_CONFIG_PCIAHB_BRIDGE 0x00001000 +#define AR5315_CONFIG_SPI 0x00008000 /* SPI byteswap */ +#define AR5315_CONFIG_CPU_DRAM 0x00010000 +#define AR5315_CONFIG_CPU_PCI 0x00020000 +#define AR5315_CONFIG_CPU_MMR 0x00040000 +#define AR5315_CONFIG_BIG 0x00000400 /* -- cgit v1.2.3