From 53c474abbdfef8eb3499e2d10c9ad491788b8a72 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 6 May 2018 10:20:11 +0200 Subject: ath79: add new OF only target for QCA MIPS silicon This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin --- ...-ath79-export-switch-MDIO-reference-clock.patch | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch (limited to 'target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch') diff --git a/target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch b/target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch new file mode 100644 index 0000000000..6530344ce3 --- /dev/null +++ b/target/linux/ath79/patches-4.14/0033-MIPS-ath79-export-switch-MDIO-reference-clock.patch @@ -0,0 +1,54 @@ +From: Felix Fietkau +Date: Tue, 6 Mar 2018 13:27:28 +0100 +Subject: [PATCH] MIPS: ath79: export switch MDIO reference clock + +On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz +clock. If that feature is not used, it defaults to the main reference clock, +like on all other SoC. + +Signed-off-by: Felix Fietkau +--- + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -41,6 +41,7 @@ static const char * const clk_names[ATH7 + [ATH79_CLK_DDR] = "ddr", + [ATH79_CLK_AHB] = "ahb", + [ATH79_CLK_REF] = "ref", ++ [ATH79_CLK_MDIO] = "mdio", + }; + + static const char * __init ath79_clk_name(int type) +@@ -341,6 +342,10 @@ static void __init ar934x_clocks_init(vo + ath79_set_clk(ATH79_CLK_DDR, ddr_rate); + ath79_set_clk(ATH79_CLK_AHB, ahb_rate); + ++ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); ++ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) ++ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); ++ + iounmap(dpll_base); + } + +@@ -687,6 +692,9 @@ static void __init ath79_clocks_init_dt( + else if (of_device_is_compatible(np, "qca,qca9560-pll")) + qca956x_clocks_init(pll_base); + ++ if (!clks[ATH79_CLK_MDIO]) ++ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; ++ + if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { + pr_err("%pOF: could not register clk provider\n", np); + goto err_iounmap; +--- a/include/dt-bindings/clock/ath79-clk.h ++++ b/include/dt-bindings/clock/ath79-clk.h +@@ -14,7 +14,8 @@ + #define ATH79_CLK_DDR 1 + #define ATH79_CLK_AHB 2 + #define ATH79_CLK_REF 3 ++#define ATH79_CLK_MDIO 4 + +-#define ATH79_CLK_END 4 ++#define ATH79_CLK_END 5 + + #endif /* __DT_BINDINGS_ATH79_CLK_H */ -- cgit v1.2.3