From 9b90dc05f58c619962e69e36d275b6ea56893496 Mon Sep 17 00:00:00 2001 From: Anderson Vulczak Date: Sat, 5 Oct 2019 10:44:55 -0300 Subject: ath79: add support for TP-Link Archer C6 v2 (US) and A6 (US/TW) This patch is based on #1689 and adds support for TP-Link Archer C6 v2 (US) and A6 (US/TW). The hardware is the same as EU and RU variant, except for GPIOs (LEDS/Buttons), flash(chip/partitions) and UART being available on the board. - SOC: Qualcomm QCA9563 @ 775MHz - Flash: GigaDevice GD25Q127CS1G (16MiB) - RAM: Zentel A3R1GE40JBF (128 MiB DDR2) - Ethernet: Qualcomm QCA8337N: 4x 1Gbps LAN + 1x 1Gbps WAN - Wireless: - 2.4GHz (bgn) QCA9563 integrated (3x3) - 5GHz (ac) Qualcomm QCA9886 (2x2) - Button: 1x power, 1x reset, 1x wps - LED: 6x LEDs: power, wlan2g, wlan5g, lan, wan, wps - UART: 115200, 8n1 (header available on board) Known issues: - Wireless: 5GHz is known to have lower RSSI signal, it affects speed and range. Flash instructions: Upload openwrt-ath79-generic-tplink_archer-c6-v2-us-squashfs-factory.bin via the router Web interface. Flash instruction using tftp recovery: 1. Connect the computer to one of the LAN ports of the router 2. Set the computer IP to 192.168.0.66 3. Start a tftp server with the OpenWrt factory image in the tftp root directory renamed to ArcherA6v2_tp_recovery.bin. 4. Connect power cable to router, press and hold the reset button and turn the router on 5. Keep the reset button pressed until the WPS LED lights up 6. Wait ~150 seconds to complete flashing Flash partitioning: I've followed #1689 for defining the partition layout for this patch. The partition named as "tplink" @ 0xfd0000 is marked as read only as it is where some config for stock firmware are stored. On stock firmware those stock partitions starts at 0xfd9400 however I had not been able to make it functional starting on the same address as on stock fw, so it has been partitioned following #1689 and not the stock partition layout for this specific partition. Due to that firmware/rootfs partition lenght is 0xf80000 and not 0xf89400 as stock. According to the GPL code, the EU/RU/JP variant does have different GPIO pins assignment to LEDs and buttons, also the flash memory layout is different. GPL Source Code: https://static.tp-link.com/resources/gpl/gpl-A6v2_us.tar.gz Signed-off-by: Anderson Vulczak [wrap commit message, remove soft_ver change for C6 v2 EU, move LED aliases to DTS files, remove dts-v1 in DTSI, node/property reorder in DTSI] Signed-off-by: Adrian Schmutzler --- .../ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target/linux/ath79/generic/base-files/etc/hotplug.d') diff --git a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 97233fa0e4..062caf6ad5 100644 --- a/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -146,7 +146,8 @@ case "$FIRMWARE" in tplink,archer-c59-v2|\ tplink,archer-c60-v1|\ tplink,archer-c60-v2|\ - tplink,archer-c6-v2) + tplink,archer-c6-v2|\ + tplink,archer-c6-v2-us) caldata_extract "art" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary mac 0x8) -1) ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \ -- cgit v1.2.3