From abc7ed2c58860fc1363129efbe9e8c60f81a802c Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Sat, 29 Dec 2018 17:22:32 +0800 Subject: ath79: add support for D-Link DIR-859 A1 Hardware spec of DIR-859 A1: SoC: QCA9563 DRAM: 64MB DDR2 Flash: 16MB SPI-NOR Switch: QCA8337N WiFi 5.8GHz: QCA9880 USB is supported on the PCB but not connected. Flash instructions: 1. Upgrade the factory.bin through the factory web interface or the u-boot failsafe interface. The firmware will boot up correctly for the first time. Do not power off the device after OpenWrt has booted. Otherwise the u-boot will enter failsafe mode as the checksum of the firmware has been changed. 2. Upgrade the sysupgrade.bin in OpenWrt. After upgrading completes the u-boot won't complain about the firmware checksum and it's OK to use now. 3. If you powered off the device before upgrading the sysupgrade.bin, just upgrade the factory.bin through the u-boot failsafe interface and then goto step 2. Signed-off-by: Weijie Gao [squash commits, use common seama recipes, sync factory image recipe with ramips version] Signed-off-by: Mathias Kresin --- .../linux/ath79/dts/qca9563_dlink_dir-859-a1.dts | 177 +++++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts (limited to 'target/linux/ath79/dts') diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts b/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts new file mode 100644 index 0000000000..23b4cc5126 --- /dev/null +++ b/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca956x.dtsi" + +/ { + model = "D-Link DIR-859 A1"; + compatible = "dlink,dir-859-a1", "qca,qca9563"; + + aliases { + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + wps { + label = "dir-859-a1:green:wps"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + }; + + power: power { + label = "dir-859-a1:green:power"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + + internet { + label = "dir-859-a1:green:internet"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + wlan { + label = "dir-859-a1:green:wlan"; + gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + wps { + linux,code = ; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + reset { + linux,code = ; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + #size-cells = <0>; + + gpio_switch_reset { + gpio-export,name = "dir-859-a1:reset:switch"; + gpio-export,output = <1>; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&spi { + num-cs = <1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x40000>; + read-only; + }; + + partition@40000 { + label = "bdcfg"; + reg = <0x040000 0x10000>; + read-only; + }; + + partition@50000 { + label = "devdata"; + reg = <0x050000 0x10000>; + read-only; + }; + + partition@60000 { + label = "devconf"; + reg = <0x060000 0x10000>; + read-only; + }; + + partition@70000 { + compatible = "seama"; + label = "firmware"; + reg = <0x070000 0xf80000>; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy-mask = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "sgmii"; + + qca,ar8327-initvals = < + 0x04 0x00080080 /* PORT0 PAD MODE CTRL */ + 0x10 0x81000080 /* POWER_ON_STRIP */ + 0x50 0xcc35cc35 /* LED_CTRL0 */ + 0x54 0xcb37cb37 /* LED_CTRL1 */ + 0x58 0x00000000 /* LED_CTRL2 */ + 0x5c 0x00f3cf00 /* LED_CTRL3 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001919>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&wmac { + status = "okay"; + qca,no-eeprom; +}; -- cgit v1.2.3