From 84451173f08e7af9e47c85c1a0cd8e041f4ec568 Mon Sep 17 00:00:00 2001 From: Jihoon Han Date: Fri, 1 Oct 2021 14:53:06 +0900 Subject: ath79: add support for Dongwon T&I DW02-412H Dongwon T&I DW02-412H is a 2.4/5GHz band 11ac (WiFi-5) router, based on Qualcomm Atheros QCA9557. Specifications -------------- - SoC: Qualcomm Atheros QCA9557-AT4A - RAM: DDR2 128MB - Flash: SPI NOR 2MB (Winbond W25Q16DVSSIG / ESMT F25L16PA(2S)) + NAND 64/128MB - WiFi: - 2.4GHz: QCA9557 WMAC - 5GHz: QCA9882-BR4A - Ethernet: 5x 10/100/1000Mbps - Switch: QCA8337N-AL3C - USB: 1x USB 2.0 - UART: - JP2: 3.3V, TX, RX, GND (3.3V is the square pad) / 115200 8N1 Installation -------------- 1. Connect a serial interface to UART header and interrupt the autostart of kernel. 2. Transfer the factory image via TFTP and write it to the NAND flash. 3. Update U-Boot environment variable. > tftpboot 0x81000000 -factory.img > nand erase 0x1000000 > nand write 0x81000000 0x1000000 ${filesize} > setenv bootpart 2 > saveenv Revert to stock firmware -------------- 1. Revert to stock U-Boot environment variable. > setenv bootpart 1 > saveenv MAC addresses as verified by OEM firmware -------------- WAN: *:XX (label) LAN: *:XX + 1 2.4G: *:XX + 3 5G: *:XX + 4 The label MAC address was found in art 0x0. Credits -------------- Credit goes to the @manatails who first developed how to port OpenWRT to this device and had a significant impact on this patch. And thanks to @adschm and @mans0n for guiding me to revise the code in many ways. Signed-off-by: Jihoon Han Reviewed-by: Sungbo Eo Tested-by: Sungbo Eo --- .../ath79/dts/qca9557_dongwon_dw02-412h-128m.dts | 34 ++++ .../ath79/dts/qca9557_dongwon_dw02-412h-64m.dts | 34 ++++ .../linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi | 175 +++++++++++++++++++++ 3 files changed, 243 insertions(+) create mode 100644 target/linux/ath79/dts/qca9557_dongwon_dw02-412h-128m.dts create mode 100644 target/linux/ath79/dts/qca9557_dongwon_dw02-412h-64m.dts create mode 100644 target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi (limited to 'target/linux/ath79/dts') diff --git a/target/linux/ath79/dts/qca9557_dongwon_dw02-412h-128m.dts b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h-128m.dts new file mode 100644 index 0000000000..2308d82af9 --- /dev/null +++ b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h-128m.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca9557_dongwon_dw02-412h.dtsi" + +/ { + model = "Dongwon T&I DW02-412H (128M)"; + compatible = "dongwon,dw02-412h-128m", "qca,qca9557"; +}; + +&nand { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "current"; + reg = <0x0 0x1000000>; + read-only; + }; + + partition@1000000 { + label = "kernel"; + reg = <0x1000000 0x800000>; + }; + + partition@1800000 { + label = "ubi"; + reg = <0x1800000 0x6800000>; + }; + }; +}; diff --git a/target/linux/ath79/dts/qca9557_dongwon_dw02-412h-64m.dts b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h-64m.dts new file mode 100644 index 0000000000..2420dc11a9 --- /dev/null +++ b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h-64m.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca9557_dongwon_dw02-412h.dtsi" + +/ { + model = "Dongwon T&I DW02-412H (64M)"; + compatible = "dongwon,dw02-412h-64m", "qca,qca9557"; +}; + +&nand { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "current"; + reg = <0x0 0x1000000>; + read-only; + }; + + partition@1000000 { + label = "kernel"; + reg = <0x1000000 0x800000>; + }; + + partition@1800000 { + label = "ubi"; + reg = <0x1800000 0x2800000>; + }; + }; +}; diff --git a/target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi new file mode 100644 index 0000000000..fd56983432 --- /dev/null +++ b/target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca955x.dtsi" + +#include +#include + +/ { + aliases { + led-boot = &led_wan; + led-failsafe = &led_wan; + led-upgrade = &led_wan; + }; + + keys { + compatible = "gpio-keys"; + + wps { + label = "WPS button"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + reset { + label = "Reset button"; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_wan: wan { + label = "green:wan"; + gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + + wlan { + label = "green:wlan"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x040000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x040000 0x010000>; + }; + + partition@50000 { + label = "log"; + reg = <0x050000 0x010000>; + read-only; + }; + + partition@60000 { + label = "recoverk"; + reg = <0x060000 0x0e0000>; + read-only; + }; + + partition@140000 { + label = "recoverr"; + reg = <0x140000 0x090000>; + read-only; + }; + + partition@1d0000 { + label = "nvram"; + reg = <0x1d0000 0x010000>; + read-only; + }; + + partition@1e0000 { + label = "nvbackup"; + reg = <0x1e0000 0x010000>; + read-only; + }; + + art: partition@1f0000 { + label = "art"; + reg = <0x1f0000 0x010000>; + read-only; + }; + }; + }; +}; + +&pcie0 { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0 0 0 0 0>; + }; +}; + +&wmac { + status = "okay"; + + mtd-cal-data = <&art 0x1000>; + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <3>; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x07600000 /* PORT0 PAD MODE CTRL */ + 0x50 0xcf37cf37 /* LED Control Register 0 */ + 0x54 0x00000000 /* LED Control Register 1 */ + 0x58 0x00000000 /* LED Control Register 2 */ + 0x5c 0x0030c300 /* LED Control Register 3 */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + phy-handle = <&phy0>; + pll-data = <0xa6000000 0x00000101 0x00001616>; + + gmac-config { + device = <&gmac>; + rgmii-enabled = <1>; + }; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; +}; -- cgit v1.2.3