From 3c3eaa57d9806dccae9f130cf608079f67097bed Mon Sep 17 00:00:00 2001 From: Marcin Jurkowski Date: Tue, 11 Dec 2018 16:14:21 +0100 Subject: ath79: add support for TP-Link TL-WR842N/ND v1 router This ports support for TP-Link TL-WR842N/ND v1 from ar71xx. CPU: Atheros AR7241 400 MHz RAM: 32 MiB FLASH: 8 MiB PORTS: 4 Port 100/10 Switch, 1 Port 100/10 Wan WiFi: Atheros AR9287 LED: SYS, WiFi, LAN, WAN, 3G, QSS BTN: WiFi, Reset/WPS AR71xx target used "tl-mr3420" as board id so force flag is needed if upgrading from old target. Signed-off-by: Marcin Jurkowski Signed-off-by: Christian Lamparter [trivial cleanup] --- .../linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts | 164 +++++++++++++++++++++ 1 file changed, 164 insertions(+) create mode 100644 target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts (limited to 'target/linux/ath79/dts') diff --git a/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts new file mode 100644 index 0000000000..282446b1e1 --- /dev/null +++ b/target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "ar7241.dtsi" + +/ { + compatible = "tplink,tl-wr842n-v1", "qca,ar7241"; + model = "TP-Link TL-WR842N/ND v1"; + + aliases { + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + rfkill { + label = "rfkill"; + linux,code = ; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_system: system { + label = "tp-link:green:system"; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + + qss { + label = "tp-link:green:qss"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + + led3g { + label = "tp-link:green:3g"; + gpios = <&gpio 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&hub_port>; + linux,default-trigger = "usbport"; + }; + }; + + ath9k-leds { + compatible = "gpio-leds"; + + wlan { + label = "tp-link:green:wlan"; + gpios = <&ath9k 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; + + gpio-export { + compatible = "gpio-export"; + + gpio_usb_power { + gpio-export,name = "tp-link:power:usb"; + gpio-export,output = <1>; + gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&usb { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_port: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + status = "okay"; + num-cs = <1>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot: partition@0 { + reg = <0x0 0x20000>; + label = "u-boot"; + read-only; + }; + + partition@20000 { + compatible = "tplink,firmware"; + reg = <0x20000 0x7d0000>; + label = "firmware"; + }; + + partition@7f0000 { + reg = <0x7f0000 0x10000>; + label = "art"; + read-only; + }; + }; + }; +}; + +&pcie { + status = "okay"; + + ath9k: wifi@0,0 { + compatible = "pci168c,002e"; + reg = <0x0000 0 0 0 0>; + #gpio-cells = <2>; + gpio-controller; + qca,no-eeprom; + mtd-mac-address = <&uboot 0x1fc00>; + }; +}; + +ð0 { + status = "okay"; + + mtd-mac-address = <&uboot 0x1fc00>; + mtd-mac-address-increment = <(-1)>; +}; + +ð1 { + status = "okay"; + + mtd-mac-address = <&uboot 0x1fc00>; + mtd-mac-address-increment = <1>; +}; + +&gpio { + status = "okay"; +}; + +&uart { + status = "okay"; +}; -- cgit v1.2.3