From 0ff5785c5d5e57d99acb8da06d2c08903448b663 Mon Sep 17 00:00:00 2001 From: Mathias Kresin Date: Tue, 8 May 2018 07:22:38 +0200 Subject: ath79: fix dts files Add the SoC compatible to the individual dts files. Rename the dts files to match the common pattern. Remove dts files wich aren't used and no image in ar71xx exists. Signed-off-by: Mathias Kresin --- .../ath79/dts/qca9558_openmesh_om5p-ac-v2.dts | 176 +++++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts (limited to 'target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts') diff --git a/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts new file mode 100644 index 0000000000..974b1c61f0 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "qca9557.dtsi" + +/ { + compatible = "openmesh,om5p-ac-v2", "qca,qca9557"; + model = "OpenMesh OM5P-AC V2"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + extosc: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "ref"; + clock-frequency = <40000000>; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "om5pac:blue:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wifi_green { + label = "om5pac:green:wifi"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wifi_yellow { + label = "om5pac:yellow:wifi"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wifi_red { + label = "om5pac:red:wifi"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "reset"; + linux,code = ; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-export { + compatible = "gpio-export"; + #size-cells = <0>; + + gpio_pa_dcdc { + gpio-export,name = "om5pac:pa_dcdc"; + gpio-export,output = <1>; + gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + }; + gpio_pa_high { + gpio-export,name = "om5pac:pa_high"; + gpio-export,output = <1>; + gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinmux { + pinmux_pa_dcdc_pins { + pinctrl-single,bits = <0x0 0xff00 0x0>; + }; + + pinmux_pa_high_pins { + pinctrl-single,bits = <0x10 0xff 0x0>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&uart { + status = "okay"; +}; + +&pll { + clocks = <&extosc>; +}; + +&spi { + status = "okay"; + num-cs = <1>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l12805d"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x040000>; + read-only; + }; + + partition@1 { + label = "u-boot-env"; + reg = <0x040000 0x010000>; + }; + + partition@2 { + label = "firmware"; + reg = <0x850000 0x7a0000>; + }; + + partition@3 { + label = "ART"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii-id"; + }; +}; + +&mdio1 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + phy-mode = "sgmii"; + }; +}; + +ð0 { + status = "okay"; + + phy-handle = <&phy4>; + phy-mode = "rgmii"; +}; + +ð1 { + status = "okay"; + + phy-handle = <&phy1>; + phy-mode = "sgmii"; +}; -- cgit v1.2.3