From a9360452f0130bb39a8e732334a174cc3f8991fd Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Mon, 15 Jul 2019 19:43:31 +0800 Subject: ath79: add support for Qihoo C301 Specifications: - SoC: AR9344 - RAM: 128MB - Flash: 2 * 16MB (MX25L12845) - Ethernet: 2 * FE LAN & 1 * FE WAN - WiFi: 2.4G: AR9344 5G: QCA9882 Flash instruction: 1. Hold reset and power up the router 2. Set your IP to 192.168.1.x 3. Open 192.168.1.1 and upload the generated *factory* firmware Signed-off-by: Chuanhong Guo --- target/linux/ath79/dts/ar9344_qihoo_c301.dts | 236 +++++++++++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 target/linux/ath79/dts/ar9344_qihoo_c301.dts (limited to 'target/linux/ath79/dts/ar9344_qihoo_c301.dts') diff --git a/target/linux/ath79/dts/ar9344_qihoo_c301.dts b/target/linux/ath79/dts/ar9344_qihoo_c301.dts new file mode 100644 index 0000000000..746c7f588e --- /dev/null +++ b/target/linux/ath79/dts/ar9344_qihoo_c301.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "ar9344.dtsi" + +/ { + model = "Qihoo 360 C301"; + compatible = "qihoo,c301"; + + aliases { + led-boot = &led_wlan_g; + led-failsafe = &led_wlan_o; + led-upgrade = &led_wlan_o; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&jtag_disable_pins>; + + led_wlan_g: wlan_g { + label = "c301:green:wlan"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + }; + + led_wlan_o: wlan_o { + label = "c301:orange:wlan"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + linux,code = ; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + reg_eth_led_vbus { + compatible = "regulator-fixed"; + regulator-name = "eth_led_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio 18 GPIO_ACTIVE_LOW>; + }; + + reg_usb_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio 19 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinmux { + pmx_spi_cs1: pinmux_spi_cs1 { + pinctrl-single,bits = <0xc 0x07 0xff>; + }; + + pmx_led_switch: pinmux_led_switch { + pinctrl-single,bits = <0x0 0x2b2a2d00 0xffffff00>; + }; +}; + +&ref { + clock-frequency = <40000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; + + gpio_ext_lna0 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "c301:ext:lna0"; + }; + + gpio_ext_lna1 { + gpio-hog; + gpios = <15 0>; + output-high; + line-name = "c301:ext:lna1"; + }; +}; + +&builtin_switch { + pinctrl-names = "default"; + pinctrl-0 = <&pmx_led_switch>; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&pmx_spi_cs1>; + status = "okay"; + + num-cs = <2>; + cs-gpios= <0>, <0>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot: partition@0 { + label = "u-boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "devdata"; + reg = <0x50000 0x10000>; + read-only; + }; + + partition@60000 { + label = "devconf"; + reg = <0x60000 0x10000>; + read-only; + }; + + partition@70000 { + compatible = "seama"; + label = "firmware"; + reg = <0x70000 0xf60000>; + }; + + partition@fd0000 { + label = "warm_start"; + reg = <0xfd0000 0x10000>; + read-only; + }; + + partition@fe0000 { + label = "action_image_config"; + reg = <0xfe0000 0x10000>; + }; + + partition@ff0000 { + label = "radiocfg"; + reg = <0xff0000 0x10000>; + read-only; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware2"; + reg = <0x0 0xf00000>; + }; + + partition@f00000 { + label = "privatedata"; + reg = <0xf00000 0x100000>; + read-only; + }; + }; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0 0 0 0 0>; + }; +}; + +&wmac { + status = "okay"; + qca,no-eeprom; +}; + +ð1 { + status = "okay"; + gmac-config { + device = <&gmac>; + switch-phy-swap = <1>; + switch-only-mode = <1>; + }; +}; + +ð0 { + status = "okay"; + phy-handle = <&swphy0>; +}; -- cgit v1.2.3