From e58cd453d58b20c6a6f34d3591640aa19aa14d25 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 4 Feb 2022 15:57:50 +0200 Subject: at91: add kernel support for sama7g5 soc Add kernel support for SAMA7G5 by back-porting mainline kernel patches. Among SAMA7G5 features could be remembered: - ARM Cortex-A7 - double data rate multi-port dynamic RAM controller supporting DDR2, DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz - peripherals for audio, video processing - 1 gigabit + 1 megabit Ethernet controllers - 6 CAN controllers - trust zone support - DVFS for CPU - criptography IPs Signed-off-by: Claudiu Beznea --- ...-atmel-isc-move-the-formats-list-into-pro.patch | 449 +++++++++++++++++++++ 1 file changed, 449 insertions(+) create mode 100644 target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch (limited to 'target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch') diff --git a/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch b/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch new file mode 100644 index 0000000000..cce3fabc4c --- /dev/null +++ b/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch @@ -0,0 +1,449 @@ +From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 13 Apr 2021 12:57:22 +0200 +Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into + product specific code + +The list of input and output formats has to be product specific. +Move this list into the product specific code. +Have pointers to these arrays inside the device struct. + +Signed-off-by: Eugen Hristev +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/atmel/atmel-isc-base.c | 167 ++---------------- + drivers/media/platform/atmel/atmel-isc.h | 12 +- + .../media/platform/atmel/atmel-sama5d2-isc.c | 136 ++++++++++++++ + 3 files changed, 165 insertions(+), 150 deletions(-) + +diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c +index 67c16ca17672..90a62d43fdb1 100644 +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 0644); + MODULE_PARM_DESC(sensor_preferred, + "Sensor is preferred to output the specified format (1-on 0-off), default 1"); + +-/* This is a list of the formats that the ISC can *output* */ +-const struct isc_format controller_formats[] = { +- { +- .fourcc = V4L2_PIX_FMT_ARGB444, +- }, +- { +- .fourcc = V4L2_PIX_FMT_ARGB555, +- }, +- { +- .fourcc = V4L2_PIX_FMT_RGB565, +- }, +- { +- .fourcc = V4L2_PIX_FMT_ABGR32, +- }, +- { +- .fourcc = V4L2_PIX_FMT_XBGR32, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUV420, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUYV, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUV422P, +- }, +- { +- .fourcc = V4L2_PIX_FMT_GREY, +- }, +- { +- .fourcc = V4L2_PIX_FMT_Y10, +- }, +-}; +- +-/* This is a list of formats that the ISC can receive as *input* */ +-struct isc_format formats_list[] = { +- { +- .fourcc = V4L2_PIX_FMT_SBGGR8, +- .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_BGBG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGBRG8, +- .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_GBGB, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGRBG8, +- .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_GRGR, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SRGGB8, +- .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SBGGR10, +- .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGBRG10, +- .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_GBGB, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGRBG10, +- .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_GRGR, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SRGGB10, +- .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SBGGR12, +- .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_BGBG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGBRG12, +- .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_GBGB, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SGRBG12, +- .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_GRGR, +- }, +- { +- .fourcc = V4L2_PIX_FMT_SRGGB12, +- .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, +- .cfa_baycfg = ISC_BAY_CFG_RGRG, +- }, +- { +- .fourcc = V4L2_PIX_FMT_GREY, +- .mbus_code = MEDIA_BUS_FMT_Y8_1X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- }, +- { +- .fourcc = V4L2_PIX_FMT_YUYV, +- .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- }, +- { +- .fourcc = V4L2_PIX_FMT_RGB565, +- .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, +- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, +- }, +- { +- .fourcc = V4L2_PIX_FMT_Y10, +- .mbus_code = MEDIA_BUS_FMT_Y10_1X10, +- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, +- }, +- +-}; +- + #define ISC_IS_FORMAT_RAW(mbus_code) \ + (((mbus_code) & 0xf000) == 0x3000) + +@@ -919,24 +788,25 @@ static int isc_querycap(struct file *file, void *priv, + static int isc_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) + { ++ struct isc_device *isc = video_drvdata(file); + u32 index = f->index; + u32 i, supported_index; + +- if (index < ARRAY_SIZE(controller_formats)) { +- f->pixelformat = controller_formats[index].fourcc; ++ if (index < isc->controller_formats_size) { ++ f->pixelformat = isc->controller_formats[index].fourcc; + return 0; + } + +- index -= ARRAY_SIZE(controller_formats); ++ index -= isc->controller_formats_size; + + supported_index = 0; + +- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { +- if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) || +- !formats_list[i].sd_support) ++ for (i = 0; i < isc->formats_list_size; i++) { ++ if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) || ++ !isc->formats_list[i].sd_support) + continue; + if (supported_index == index) { +- f->pixelformat = formats_list[i].fourcc; ++ f->pixelformat = isc->formats_list[i].fourcc; + return 0; + } + supported_index++; +@@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct file *file, void *fh, + if (isc->user_formats[i]->fourcc == fsize->pixel_format) + ret = 0; + +- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) +- if (controller_formats[i].fourcc == fsize->pixel_format) ++ for (i = 0; i < isc->controller_formats_size; i++) ++ if (isc->controller_formats[i].fourcc == fsize->pixel_format) + ret = 0; + + if (ret) +@@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struct file *file, void *fh, + if (isc->user_formats[i]->fourcc == fival->pixel_format) + ret = 0; + +- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) +- if (controller_formats[i].fourcc == fival->pixel_format) ++ for (i = 0; i < isc->controller_formats_size; i++) ++ if (isc->controller_formats[i].fourcc == fival->pixel_format) + ret = 0; + + if (ret) +@@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier, + v4l2_ctrl_handler_free(&isc->ctrls.handler); + } + +-static struct isc_format *find_format_by_code(unsigned int code, int *index) ++static struct isc_format *find_format_by_code(struct isc_device *isc, ++ unsigned int code, int *index) + { +- struct isc_format *fmt = &formats_list[0]; ++ struct isc_format *fmt = &isc->formats_list[0]; + unsigned int i; + +- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { ++ for (i = 0; i < isc->formats_list_size; i++) { + if (fmt->mbus_code == code) { + *index = i; + return fmt; +@@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_device *isc) + struct isc_format *fmt; + struct v4l2_subdev *subdev = isc->current_subdev->sd; + unsigned int num_fmts, i, j; +- u32 list_size = ARRAY_SIZE(formats_list); ++ u32 list_size = isc->formats_list_size; + struct v4l2_subdev_mbus_code_enum mbus_code = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; +@@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_device *isc) + NULL, &mbus_code)) { + mbus_code.index++; + +- fmt = find_format_by_code(mbus_code.code, &i); ++ fmt = find_format_by_code(isc, mbus_code.code, &i); + if (!fmt) { + v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n", + mbus_code.code); +@@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_device *isc) + if (!isc->user_formats) + return -ENOMEM; + +- fmt = &formats_list[0]; ++ fmt = &isc->formats_list[0]; + for (i = 0, j = 0; i < list_size; i++) { + if (fmt->sd_support) + isc->user_formats[j++] = fmt; +diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h +index 24006327c5e4..b34737c09a5b 100644 +--- a/drivers/media/platform/atmel/atmel-isc.h ++++ b/drivers/media/platform/atmel/atmel-isc.h +@@ -236,6 +236,12 @@ struct isc_reg_offsets { + * specific v4l2 controls. + * + * @offsets: struct holding the product specific register offsets ++ * @controller_formats: pointer to the array of possible formats that the ++ * controller can output ++ * @formats_list: pointer to the array of possible formats that can ++ * be used as an input to the controller ++ * @controller_formats_size: size of controller_formats array ++ * @formats_list_size: size of formats_list array + */ + struct isc_device { + struct regmap *regmap; +@@ -317,10 +323,12 @@ struct isc_device { + }; + + struct isc_reg_offsets offsets; ++ const struct isc_format *controller_formats; ++ struct isc_format *formats_list; ++ u32 controller_formats_size; ++ u32 formats_list_size; + }; + +-extern struct isc_format formats_list[]; +-extern const struct isc_format controller_formats[]; + extern const struct regmap_config isc_regmap_config; + extern const struct v4l2_async_notifier_operations isc_async_ops; + +diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +index 86704a1a24b9..b8c1b57ed820 100644 +--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c ++++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c +@@ -54,6 +54,137 @@ + + #define ISC_CLK_MAX_DIV 255 + ++/* This is a list of the formats that the ISC can *output* */ ++static const struct isc_format sama5d2_controller_formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_ARGB444, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_ARGB555, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB565, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_ABGR32, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_XBGR32, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV422P, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_GREY, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_Y10, ++ }, ++}; ++ ++/* This is a list of formats that the ISC can receive as *input* */ ++static struct isc_format sama5d2_formats_list[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR8, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_BGBG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG8, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG8, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB8, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR10, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG10, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG10, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB10, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SBGGR12, ++ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_BGBG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGBRG12, ++ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_GBGB, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SGRBG12, ++ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_GRGR, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_SRGGB12, ++ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, ++ .cfa_baycfg = ISC_BAY_CFG_RGRG, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_GREY, ++ .mbus_code = MEDIA_BUS_FMT_Y8_1X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_RGB565, ++ .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, ++ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_Y10, ++ .mbus_code = MEDIA_BUS_FMT_Y10_1X10, ++ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, ++ }, ++ ++}; ++ + static void isc_sama5d2_config_csc(struct isc_device *isc) + { + struct regmap *regmap = isc->regmap; +@@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platform_device *pdev) + isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; + isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; + ++ isc->controller_formats = sama5d2_controller_formats; ++ isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats); ++ isc->formats_list = sama5d2_formats_list; ++ isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list); ++ + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; + +-- +2.32.0 + -- cgit v1.2.3