From d55a05fc9e92e4699f98216e0f01221796d9df9a Mon Sep 17 00:00:00 2001 From: Evgeniy Didin Date: Tue, 13 Feb 2018 17:24:25 +0300 Subject: archs38: add HSDK board Synopsys DesignWare HSDK (which stands for ARC HS Development Kit) is the latest and greatest development platform that sports quad-core ARC HS38 in real silicon. Most noticeable features of the board are: * Quad-core ARC HS38 CPU running at 1GHz * 4Gb of DDR * Built-in Vivante GPU (well supported via open source Etnaviv drivers) * Built-in Wi-Fi/Bluetooth module (RedPine RS-9113) And as usual we have: * [micro] SD-card slot * 2 USB 2.0 ports * 1Gbit Ethernet port * Built-in Digilent JTAG probe * Serial port accessible via micro-USB port For more information about HSDK board visit: https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit Signed-off-by: Evgeniy Didin CC: Alexey Brodkin CC: Hauke Mehrtens CC: John Crispin --- target/linux/archs38/image/uboot.env.txt | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 target/linux/archs38/image/uboot.env.txt (limited to 'target/linux/archs38/image/uboot.env.txt') diff --git a/target/linux/archs38/image/uboot.env.txt b/target/linux/archs38/image/uboot.env.txt new file mode 100644 index 0000000000..9ae7bd0c62 --- /dev/null +++ b/target/linux/archs38/image/uboot.env.txt @@ -0,0 +1,29 @@ +baudrate=115200 +bootargs=console=ttyS0,115200n8 root=/dev/mmcblk0p2 rootwait +bootcmd=fatload mmc 0:1 0x82000000 uImage && fatload mmc 0:1 0x81000000 hsdk.dtb && bootm 0x82000000 - 0x81000000 +bootdelay=2 +bootfile=uImage +loadaddr=0x82000000 +stderr=serial0@f0005000 +stdin=serial0@f0005000 +stdout=serial0@f0005000 +core_dccm_0=0x10 +core_dccm_1=0x6 +core_dccm_2=0x10 +core_dccm_3=0x6 +core_iccm_0=0x10 +core_iccm_1=0x6 +core_iccm_2=0x10 +core_iccm_3=0x6 +core_mask=0xF +dcache_ena=0x1 +icache_ena=0x1 +non_volatile_limit=0xE +hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; setenv dcache_ena 0x0; setenv core_iccm_1 0x7; setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0; +hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; +hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_1 0x7; setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE; +hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; +hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_1 0x7; setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE; +hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; +hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; +hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; setenv core_iccm_3 0x6; setenv core_dccm_3 0x6; -- cgit v1.2.3