From d04056e5ea64debd69b075f2fc9ed6a44a2f57a2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Thu, 11 Jan 2018 00:22:42 +0100 Subject: ar71xx: disable devicetree support While we'd like to convert ar71xx to DT-based configuration eventually, we aren't quite there yet, and shipping half-baked DT support that is not used at all wastes precious space. Saves ~120KB before LZMA, ~33KB after LZMA. Run-tested on TP-Link CPE510 and TL-WR841 v7. Signed-off-by: Matthias Schiffer --- .../patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch') diff --git a/target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch index 869fdd6dd0..03ff6c6aac 100644 --- a/target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.9/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. config ATH79_NVRAM --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c -@@ -356,6 +356,91 @@ static void __init ar934x_clocks_init(vo +@@ -358,6 +358,91 @@ static void __init ar934x_clocks_init(vo iounmap(dpll_base); } @@ -136,7 +136,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. static void __init qca955x_clocks_init(void) { unsigned long ref_rate; -@@ -451,6 +536,8 @@ void __init ath79_clocks_init(void) +@@ -453,6 +538,8 @@ void __init ath79_clocks_init(void) ar933x_clocks_init(); else if (soc_is_ar934x()) ar934x_clocks_init(); -- cgit v1.2.3