From 5b34dffcbd6175d92f871b69098e027341b6c82e Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 14 May 2016 20:24:37 +0200 Subject: ar71xx: fix DDR write buffer flushing issues with 4.4 Signed-off-by: Felix Fietkau --- ...make-ath79_ddr_ctrl_init-compatible-for-n.patch | 31 ++++++++++++++++++++++ ...low-to-pass-probe-types-via-platform-data.patch | 2 +- ...412-mtd-m25p80-zero-partition-parser-data.patch | 2 +- .../patches-4.4/431-spi-add-various-flags.patch | 4 +-- .../461-spi-add-type-field-to-spi_transfer.patch | 4 +-- .../462-mtd-m25p80-set-spi-transfer-type.patch | 2 +- .../464-spi-ath79-fix-fast-flash-read.patch | 4 +-- .../525-MIPS-ath79-enable-qca-usb-quirks.patch | 8 +++--- .../601-MIPS-ath79-add-more-register-defines.patch | 4 +-- .../patches-4.4/609-MIPS-ath79-ap136-fixes.patch | 14 +++++----- ...20-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 4 +-- 11 files changed, 55 insertions(+), 24 deletions(-) create mode 100644 target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch (limited to 'target/linux/ar71xx/patches-4.4') diff --git a/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch b/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch new file mode 100644 index 0000000000..09e6617b90 --- /dev/null +++ b/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch @@ -0,0 +1,31 @@ +From: Felix Fietkau +Date: Sat, 14 May 2016 20:20:04 +0200 +Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer + SoCs + +AR913x, AR724x and AR933x are the only SoCs where the +ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c +Invert the logic to make the code compatible with AR95xx + +Signed-off-by: Felix Fietkau +--- + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void) + { + ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); +- if (soc_is_ar71xx() || soc_is_ar934x()) { +- ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; +- ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; +- } else { ++ if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) { + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; + ath79_ddr_pci_win_base = 0; ++ } else { ++ ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; ++ ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; + } + } + EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); diff --git a/target/linux/ar71xx/patches-4.4/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-4.4/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch index 6a9132032f..04acdb6d9e 100644 --- a/target/linux/ar71xx/patches-4.4/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch +++ b/target/linux/ar71xx/patches-4.4/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch @@ -1,6 +1,6 @@ --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c -@@ -229,7 +229,9 @@ static int m25p_probe(struct spi_device +@@ -251,7 +251,9 @@ static int m25p_probe(struct spi_device ppdata.of_node = spi->dev.of_node; diff --git a/target/linux/ar71xx/patches-4.4/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-4.4/412-mtd-m25p80-zero-partition-parser-data.patch index 175acf630e..866920a249 100644 --- a/target/linux/ar71xx/patches-4.4/412-mtd-m25p80-zero-partition-parser-data.patch +++ b/target/linux/ar71xx/patches-4.4/412-mtd-m25p80-zero-partition-parser-data.patch @@ -1,6 +1,6 @@ --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c -@@ -227,6 +227,7 @@ static int m25p_probe(struct spi_device +@@ -249,6 +249,7 @@ static int m25p_probe(struct spi_device if (ret) return ret; diff --git a/target/linux/ar71xx/patches-4.4/431-spi-add-various-flags.patch b/target/linux/ar71xx/patches-4.4/431-spi-add-various-flags.patch index 5824a04284..bf5aff5c7e 100644 --- a/target/linux/ar71xx/patches-4.4/431-spi-add-various-flags.patch +++ b/target/linux/ar71xx/patches-4.4/431-spi-add-various-flags.patch @@ -1,6 +1,6 @@ --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h -@@ -690,6 +690,8 @@ struct spi_transfer { +@@ -695,6 +695,8 @@ struct spi_transfer { unsigned cs_change:1; unsigned tx_nbits:3; unsigned rx_nbits:3; @@ -9,7 +9,7 @@ #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ -@@ -735,6 +737,7 @@ struct spi_message { +@@ -740,6 +742,7 @@ struct spi_message { struct spi_device *spi; unsigned is_dma_mapped:1; diff --git a/target/linux/ar71xx/patches-4.4/461-spi-add-type-field-to-spi_transfer.patch b/target/linux/ar71xx/patches-4.4/461-spi-add-type-field-to-spi_transfer.patch index be6233c19c..6ccb632ecc 100644 --- a/target/linux/ar71xx/patches-4.4/461-spi-add-type-field-to-spi_transfer.patch +++ b/target/linux/ar71xx/patches-4.4/461-spi-add-type-field-to-spi_transfer.patch @@ -1,6 +1,6 @@ --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h -@@ -578,6 +578,12 @@ extern struct spi_master *spi_busnum_to_ +@@ -583,6 +583,12 @@ extern struct spi_master *spi_busnum_to_ /*---------------------------------------------------------------------------*/ @@ -13,7 +13,7 @@ /* * I/O INTERFACE between SPI controller and protocol drivers * -@@ -698,6 +704,7 @@ struct spi_transfer { +@@ -703,6 +709,7 @@ struct spi_transfer { u8 bits_per_word; u16 delay_usecs; u32 speed_hz; diff --git a/target/linux/ar71xx/patches-4.4/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-4.4/462-mtd-m25p80-set-spi-transfer-type.patch index 11bf9ff71b..f949235966 100644 --- a/target/linux/ar71xx/patches-4.4/462-mtd-m25p80-set-spi-transfer-type.patch +++ b/target/linux/ar71xx/patches-4.4/462-mtd-m25p80-set-spi-transfer-type.patch @@ -1,6 +1,6 @@ --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c -@@ -137,10 +137,12 @@ static int m25p80_read(struct spi_nor *n +@@ -159,10 +159,12 @@ static int m25p80_read(struct spi_nor *n flash->command[0] = nor->read_opcode; m25p_addr2cmd(nor, from, flash->command); diff --git a/target/linux/ar71xx/patches-4.4/464-spi-ath79-fix-fast-flash-read.patch b/target/linux/ar71xx/patches-4.4/464-spi-ath79-fix-fast-flash-read.patch index f8ae4e00bb..03483e82a6 100644 --- a/target/linux/ar71xx/patches-4.4/464-spi-ath79-fix-fast-flash-read.patch +++ b/target/linux/ar71xx/patches-4.4/464-spi-ath79-fix-fast-flash-read.patch @@ -1,6 +1,6 @@ --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c -@@ -137,6 +137,9 @@ static int m25p80_read(struct spi_nor *n +@@ -159,6 +159,9 @@ static int m25p80_read(struct spi_nor *n flash->command[0] = nor->read_opcode; m25p_addr2cmd(nor, from, flash->command); @@ -25,7 +25,7 @@ while (len--) { --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h -@@ -705,6 +705,7 @@ struct spi_transfer { +@@ -710,6 +710,7 @@ struct spi_transfer { u16 delay_usecs; u32 speed_hz; enum spi_transfer_type type; diff --git a/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch b/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch index 0e33674adf..61b6b4ee16 100644 --- a/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch +++ b/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch @@ -29,7 +29,9 @@ - u32 bootstrap; + void __iomem *phy_reg; + u32 t; -+ + +- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); +- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) + phy_reg = ioremap(base, 4); + if (!phy_reg) + return; @@ -41,9 +43,7 @@ + + iounmap(phy_reg); +} - -- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) ++ +static void ar934x_usb_reset_notifier(struct platform_device *pdev) +{ + if (pdev->id != -1) diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch index 0126f6a3b9..c5035778a2 100644 --- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch @@ -155,7 +155,7 @@ +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) -+ + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) @@ -188,7 +188,7 @@ +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) - ++ +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) diff --git a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch index 4d7902e166..5d9d802eda 100644 --- a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch +++ b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch @@ -135,7 +135,8 @@ +static void __init ap136_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ + +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), @@ -150,8 +151,7 @@ + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); - --static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++ + ath79_register_mdio(0, 0x0); + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); + @@ -211,16 +211,16 @@ + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; + ap136_ar8327_pad0_cfg.sgmii_delay_en = true; -+ + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; + ap136_ar8327_pad6_cfg.txclk_delay_en = true; + ap136_ar8327_pad6_cfg.rxclk_delay_en = true; + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; - -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); ++ + ath79_eth0_pll_data.pll_1000 = 0x56000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch index 6fd6dafd47..08a684becd 100644 --- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -335,10 +335,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. + status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS); + + if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) { -+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE); ++ ath79_ddr_wb_flush(3); + generic_handle_irq(ATH79_IP2_IRQ(0)); + } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) { -+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC); ++ ath79_ddr_wb_flush(4); + generic_handle_irq(ATH79_IP2_IRQ(1)); + } else { + spurious_interrupt(); -- cgit v1.2.3