From 5b34dffcbd6175d92f871b69098e027341b6c82e Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 14 May 2016 20:24:37 +0200 Subject: ar71xx: fix DDR write buffer flushing issues with 4.4 Signed-off-by: Felix Fietkau --- .../ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch') diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch index 0126f6a3b9..c5035778a2 100644 --- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch @@ -155,7 +155,7 @@ +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) -+ + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) @@ -188,7 +188,7 @@ +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) - ++ +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) -- cgit v1.2.3