From 5b34dffcbd6175d92f871b69098e027341b6c82e Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 14 May 2016 20:24:37 +0200 Subject: ar71xx: fix DDR write buffer flushing issues with 4.4 Signed-off-by: Felix Fietkau --- ...make-ath79_ddr_ctrl_init-compatible-for-n.patch | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch (limited to 'target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch') diff --git a/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch b/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch new file mode 100644 index 0000000000..09e6617b90 --- /dev/null +++ b/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch @@ -0,0 +1,31 @@ +From: Felix Fietkau +Date: Sat, 14 May 2016 20:20:04 +0200 +Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer + SoCs + +AR913x, AR724x and AR933x are the only SoCs where the +ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c +Invert the logic to make the code compatible with AR95xx + +Signed-off-by: Felix Fietkau +--- + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void) + { + ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); +- if (soc_is_ar71xx() || soc_is_ar934x()) { +- ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; +- ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; +- } else { ++ if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) { + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; + ath79_ddr_pci_win_base = 0; ++ } else { ++ ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; ++ ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; + } + } + EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); -- cgit v1.2.3