From 77b81718cbcdbfd9a3615d739443fe528f88d9c2 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 27 Sep 2010 14:53:43 +0000 Subject: ar71xx: use different address in ap91_pci_fixup for the AR724[012] SoCs With this change ath9k can handle the wireless chip on the TL-WR841N v7 board which is based on the AR7241 SoC. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23130 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c index e81a01aba7..f24d4697c1 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c @@ -67,7 +67,20 @@ static void ap91_pci_fixup(struct pci_dev *dev) } /* Setup the PCI device to allow access to the internal registers */ - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); + switch (ar71xx_soc) { + case AR71XX_SOC_AR7240: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); + break; + + case AR71XX_SOC_AR7241: + case AR71XX_SOC_AR7242: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); + break; + + default: + BUG(); + } + pci_read_config_word(dev, PCI_COMMAND, &cmd); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, cmd); -- cgit v1.2.3