From 026245749a40e2d94006df8933b93ade9bfa652e Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sun, 27 May 2012 21:02:41 +0000 Subject: ar71xx: fix MII clock settings for various chips, improves ethernet stability on AR934x git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31925 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h') diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h index ec764c5c2f..881741660b 100644 --- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h @@ -322,6 +322,14 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) #define MII_CFG_CLK_DIV_14 5 #define MII_CFG_CLK_DIV_20 6 #define MII_CFG_CLK_DIV_28 7 +#define MII_CFG_CLK_DIV_34 8 +#define MII_CFG_CLK_DIV_42 9 +#define MII_CFG_CLK_DIV_50 10 +#define MII_CFG_CLK_DIV_58 11 +#define MII_CFG_CLK_DIV_66 12 +#define MII_CFG_CLK_DIV_74 13 +#define MII_CFG_CLK_DIV_82 14 +#define MII_CFG_CLK_DIV_98 15 #define MII_CFG_RESET BIT(31) #define MII_CMD_WRITE 0x0 -- cgit v1.2.3