From a6e3c605bc0e7d96b28758ee642388f10df8f1f4 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 7 Jul 2009 18:06:02 +0000 Subject: add AR7240 specific fixes for the ag71xx driver SVN-Revision: 16737 --- .../linux/ar71xx/files/arch/mips/ar71xx/devices.c | 39 ++++++++++++++++++++++ .../arch/mips/include/asm/mach-ar71xx/ar71xx.h | 3 ++ .../arch/mips/include/asm/mach-ar71xx/platform.h | 1 + 3 files changed, 43 insertions(+) (limited to 'target/linux/ar71xx/files/arch') diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c index f76dad5a9f..62969d00a4 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c @@ -289,6 +289,16 @@ static void ar71xx_set_pll_ge1(int speed) val, AR71XX_ETH1_PLL_SHIFT); } +static void ar724x_set_pll_ge0(int speed) +{ + /* TODO */ +} + +static void ar724x_set_pll_ge1(int speed) +{ + /* TODO */ +} + static void ar91xx_set_pll_ge0(int speed) { u32 val = ar71xx_get_eth_pll(0, speed); @@ -315,6 +325,16 @@ static void ar71xx_ddr_flush_ge1(void) ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); } +static void ar724x_ddr_flush_ge0(void) +{ + ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); +} + +static void ar724x_ddr_flush_ge1(void) +{ + ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); +} + static void ar91xx_ddr_flush_ge0(void) { ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); @@ -405,6 +425,10 @@ static struct platform_device ar71xx_eth1_device = { #define AR71XX_PLL_VAL_100 0x00001099 #define AR71XX_PLL_VAL_10 0x00991099 +#define AR724X_PLL_VAL_1000 0x00110000 +#define AR724X_PLL_VAL_100 0x00001099 +#define AR724X_PLL_VAL_10 0x00991099 + #define AR91XX_PLL_VAL_1000 0x1a000000 #define AR91XX_PLL_VAL_100 0x13000a44 #define AR91XX_PLL_VAL_10 0x00441099 @@ -433,6 +457,13 @@ static void __init ar71xx_init_eth_pll_data(unsigned int id) pll_100 = AR71XX_PLL_VAL_100; pll_1000 = AR71XX_PLL_VAL_1000; break; + + case AR71XX_SOC_AR7240: + pll_10 = AR724X_PLL_VAL_10; + pll_100 = AR724X_PLL_VAL_100; + pll_1000 = AR724X_PLL_VAL_1000; + break; + case AR71XX_SOC_AR9130: case AR71XX_SOC_AR9132: pll_10 = AR91XX_PLL_VAL_10; @@ -522,6 +553,14 @@ void __init ar71xx_add_device_eth(unsigned int id) pdata->has_gbit = 1; break; + case AR71XX_SOC_AR7240: + pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 + : ar724x_ddr_flush_ge0; + pdata->set_pll = id ? ar724x_set_pll_ge1 + : ar724x_set_pll_ge0; + pdata->is_ar724x = 1; + break; + case AR71XX_SOC_AR9130: pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 : ar91xx_ddr_flush_ge0; diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 4486997304..989fa52bfe 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -292,6 +292,9 @@ void ar71xx_gpio_function_disable(u32 mask); #define AR71XX_DDR_REG_FLUSH_USB 0xa4 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 + #define AR91XX_DDR_REG_FLUSH_GE0 0x7c #define AR91XX_DDR_REG_FLUSH_GE1 0x80 #define AR91XX_DDR_REG_FLUSH_USB 0x84 diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h index 55c62b7130..c305a821d0 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h @@ -28,6 +28,7 @@ struct ag71xx_platform_data { u8 has_gbit:1; u8 is_ar91xx:1; + u8 is_ar724x:1; u8 has_ar8216:1; void (* ddr_flush)(void); -- cgit v1.2.3