From 8dd455e3c4dc567c90950230ef848c3a64af3ade Mon Sep 17 00:00:00 2001 From: Julien Dusser Date: Wed, 20 Dec 2017 15:29:42 +0100 Subject: ar71xx: add more registers to ar71x_regs.h Add more registers and flags to ar71x_regs.h for QCA955x and QCA956x SoCs. Values come from Qualcomm Atheros u-boot code. Patches can be merged into 622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch Signed-off-by: Julien Dusser --- target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'target/linux/ar71xx/files/arch/mips') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c index a24cb3fce6..2d2fb6e84c 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c @@ -168,17 +168,6 @@ static int mr18_extract_sgmii_res_cal(void) return reversed_sgmii_value; } -#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x004c -#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2) -#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1) -#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0) - -#define QCA955X_GMAC_REG_SGMII_SERDES 0x0018 -#define QCA955X_SGMII_SERDES_RES_CALIBRATION BIT(23) -#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 -#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) - static void mr18_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value) { void __iomem *ethbase, *pllbase; -- cgit v1.2.3