From 22c5f96c6bb37b3368ca0f0c828cbe760f5c7f58 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 16 Mar 2016 09:27:08 +0000 Subject: ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x Some u-boot versions for QCA955x change the delays based on the link speed during boot. This usually breaks the support of other linkspeeds when OpenWrt is booted. It also conflicts with the at803x_platform_data::fixup_rgmii_tx_delay. OpenWrt has to set its own values in QCA955X_GMAC_REG_ETH_CFG. The default RGMII values from the Atheros u-boot are currently used to preset the existing mach files. These may have to be adjusted for boards using different values but which are not currently set them explicitely in OpenWrt. Signed-off-by: Sven Eckelmann Cc: Gabor Juhos Cc: Imre Kaloz Cc: Christian Beier Cc: Chris R Blake Cc: Benjamin Berg Cc: Heiner Kallweit Cc: Cezary Jackiewicz Cc: Matthias Schiffer Cc: Dirk Neukirchen Cc: Christian Mehlis Cc: Luka Perkov Cc: Felix Fietkau SVN-Revision: 49029 --- target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 2f2825f945..6445023ec4 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -830,7 +830,9 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, iounmap(base); } -void __init ath79_setup_qca955x_eth_cfg(u32 mask) +void __init ath79_setup_qca955x_eth_cfg(u32 mask, + unsigned int rxd, unsigned int rxdv, + unsigned int txd, unsigned int txe) { void __iomem *base; u32 t, m; @@ -845,6 +847,10 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask) QCA955X_ETH_CFG_RMII_GE0 | QCA955X_ETH_CFG_MII_CNTL_SPEED | QCA955X_ETH_CFG_RMII_GE0_MASTER; + m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; + m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; + m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; + m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); @@ -852,6 +858,10 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask) t &= ~m; t |= mask; + t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; + t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; + t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; + t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); -- cgit v1.2.3