From b3795d0c93d309de9be670e3d2c86b3df479ad2c Mon Sep 17 00:00:00 2001 From: Mathias Kresin Date: Sat, 21 May 2016 12:13:36 +0200 Subject: uboot-lantiq: reorder and rework patches use: - 00nn for u-boot patches - 01nn for new boards While doing the rework, the board definitions for the easy50712 and easy80920 were moved to distinct board definitions patches. Signed-off-by: Mathias Kresin --- package/boot/uboot-lantiq/Makefile | 2 +- ...014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch | 662 --------------------- ...22-MIPS-lantiq-add-default-openwrt-config.patch | 50 ++ ...lantiq-easy80920-add-support-for-NAND-SPL.patch | 61 -- ...23-MIPS-lantiq-add-default-openwrt-config.patch | 50 -- .../uboot-lantiq/patches/0023-lzma-fixup.patch | 39 ++ ...tiq-easy50712-add-openwrt-lantiq-common.h.patch | 26 - ...e-prepare-u-boot-lantiq-v2013.10-openwrt4.patch | 18 + ...tiq-easy80920-add-openwrt-lantiq-common.h.patch | 26 - .../patches/0025-arx100-cgu-fixes.patch | 148 +++++ ...PS-add-board-support-for-Arcadyan-ARV4519.patch | 242 -------- .../patches/0026-no_extern_inline.patch | 97 +++ ...PS-add-board-support-for-Arcadyan-ARV7518.patch | 242 -------- .../uboot-lantiq/patches/0027-no_weak_alias.patch | 26 + ...S-add-board-support-for-AudioCodes-MP-252.patch | 248 -------- .../patches/0028-add-gcc5-support.patch | 87 +++ ...S-add-board-support-for-AVM-FritzBox-3370.patch | 354 ----------- ...-MIPS-add-board-support-for-Gigaset-SX76X.patch | 247 -------- ...-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch | 301 ---------- ...-add-board-support-for-Arcadyan-ARV752DPW.patch | 242 -------- ...dd-board-support-for-Arcadyan-ARV752DPW22.patch | 244 -------- ...PS-add-board-support-for-Arcadyan-ARV7510.patch | 269 --------- ...dd-board-support-for-Arcadyan-ARV7510PW22.patch | 238 -------- ...e-prepare-u-boot-lantiq-v2013.10-openwrt4.patch | 18 - .../uboot-lantiq/patches/0041-lzma-fixup.patch | 44 -- .../patches/0042-arx100-cgu-fixes.patch | 148 ----- ...dd-board-support-for-Arcadyan-VGV7510KW22.patch | 346 ----------- ...dd-board-support-for-Arcadyan-ARV8539PW22.patch | 240 -------- .../patches/0045-no_extern_inline.patch | 101 ---- .../uboot-lantiq/patches/0046-no_weak_alias.patch | 28 - .../patches/0047-add-gcc5-support.patch | 93 --- ...100-MIPS-add-board-support-for-Easy-50712.patch | 306 ++++++++++ ...101-MIPS-add-board-support-for-Easy-80920.patch | 379 ++++++++++++ ...-add-board-support-for-Arcadyan-ARV4519PW.patch | 242 ++++++++ ...-add-board-support-for-Arcadyan-ARV7518PW.patch | 242 ++++++++ ...S-add-board-support-for-AudioCodes-MP-252.patch | 248 ++++++++ ...S-add-board-support-for-AVM-FritzBox-3370.patch | 354 +++++++++++ ...-MIPS-add-board-support-for-Gigaset-SX76X.patch | 247 ++++++++ ...-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch | 301 ++++++++++ ...-add-board-support-for-Arcadyan-ARV752DPW.patch | 242 ++++++++ ...dd-board-support-for-Arcadyan-ARV752DPW22.patch | 244 ++++++++ ...-add-board-support-for-Arcadyan-ARV7510PW.patch | 269 +++++++++ ...dd-board-support-for-Arcadyan-ARV7510PW22.patch | 238 ++++++++ ...dd-board-support-for-Arcadyan-VGV7510KW22.patch | 346 +++++++++++ ...dd-board-support-for-Arcadyan-ARV8539PW22.patch | 239 ++++++++ 45 files changed, 4363 insertions(+), 4471 deletions(-) create mode 100644 package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-add-default-openwrt-config.patch delete mode 100644 package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch delete mode 100644 package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch create mode 100644 package/boot/uboot-lantiq/patches/0023-lzma-fixup.patch delete mode 100644 package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch create mode 100644 package/boot/uboot-lantiq/patches/0024-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch delete mode 100644 package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch create mode 100644 package/boot/uboot-lantiq/patches/0025-arx100-cgu-fixes.patch delete mode 100644 package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch create mode 100644 package/boot/uboot-lantiq/patches/0026-no_extern_inline.patch delete mode 100644 package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch create mode 100644 package/boot/uboot-lantiq/patches/0027-no_weak_alias.patch delete mode 100644 package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch create mode 100644 package/boot/uboot-lantiq/patches/0028-add-gcc5-support.patch delete mode 100644 package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch delete mode 100644 package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch delete mode 100644 package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch delete mode 100644 package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch delete mode 100644 package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch delete mode 100644 package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch delete mode 100644 package/boot/uboot-lantiq/patches/0041-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch delete mode 100644 package/boot/uboot-lantiq/patches/0041-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch delete mode 100644 package/boot/uboot-lantiq/patches/0041-lzma-fixup.patch delete mode 100644 package/boot/uboot-lantiq/patches/0042-arx100-cgu-fixes.patch delete mode 100644 package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch delete mode 100644 package/boot/uboot-lantiq/patches/0044-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch delete mode 100644 package/boot/uboot-lantiq/patches/0045-no_extern_inline.patch delete mode 100644 package/boot/uboot-lantiq/patches/0046-no_weak_alias.patch delete mode 100644 package/boot/uboot-lantiq/patches/0047-add-gcc5-support.patch create mode 100644 package/boot/uboot-lantiq/patches/0100-MIPS-add-board-support-for-Easy-50712.patch create mode 100644 package/boot/uboot-lantiq/patches/0101-MIPS-add-board-support-for-Easy-80920.patch create mode 100644 package/boot/uboot-lantiq/patches/0102-MIPS-add-board-support-for-Arcadyan-ARV4519PW.patch create mode 100644 package/boot/uboot-lantiq/patches/0103-MIPS-add-board-support-for-Arcadyan-ARV7518PW.patch create mode 100644 package/boot/uboot-lantiq/patches/0104-MIPS-add-board-support-for-AudioCodes-MP-252.patch create mode 100644 package/boot/uboot-lantiq/patches/0105-MIPS-add-board-support-for-AVM-FritzBox-3370.patch create mode 100644 package/boot/uboot-lantiq/patches/0106-MIPS-add-board-support-for-Gigaset-SX76X.patch create mode 100644 package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch create mode 100644 package/boot/uboot-lantiq/patches/0108-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch create mode 100644 package/boot/uboot-lantiq/patches/0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch create mode 100644 package/boot/uboot-lantiq/patches/0110-MIPS-add-board-support-for-Arcadyan-ARV7510PW.patch create mode 100644 package/boot/uboot-lantiq/patches/0111-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch create mode 100644 package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch create mode 100644 package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch (limited to 'package') diff --git a/package/boot/uboot-lantiq/Makefile b/package/boot/uboot-lantiq/Makefile index 99b101f5f3..11a10f0ed7 100644 --- a/package/boot/uboot-lantiq/Makefile +++ b/package/boot/uboot-lantiq/Makefile @@ -302,7 +302,7 @@ UBOOTS:= \ arv7518pw_ram arv7518pw_nor arv7518pw_brn \ arv752dpw_ram arv752dpw_nor arv752dpw_brn \ arv752dpw22_ram arv752dpw22_nor arv752dpw22_brn \ - arv8539pw22_brn arv8539pw22_nor arv8539pw22_ram \ + arv8539pw22_brn arv8539pw22_nor arv8539pw22_ram \ gigasx76x_ram gigasx76x_nor \ acmp252_ram acmp252_nor \ easy50712_ram easy50712_nor easy50712_norspl \ diff --git a/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch index ef6eb1aaf9..1f3bf83f9e 100644 --- a/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch +++ b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch @@ -5019,491 +5019,6 @@ Signed-off-by: Daniel Schwierzeck board_early_init_f, timer_init, env_init, /* initialize environment */ ---- /dev/null -+++ b/board/lantiq/easy50712/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/lantiq/easy50712/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/lantiq/easy50712/ddr_settings.h -@@ -0,0 +1,54 @@ -+/* -+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70a -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xc02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x13c -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xd -+#define MC_DC18_VALUE 0x300 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA04 -+#define MC_DC21_VALUE 0xd00 -+#define MC_DC22_VALUE 0xd0d -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x62 -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x2d89 -+#define MC_DC30_VALUE 0x8300 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- /dev/null -+++ b/board/lantiq/easy50712/easy50712.c -@@ -0,0 +1,112 @@ -+/* -+ * Copyright (C) 2010 Thomas Langer -+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static void gpio_init(void) -+{ -+ /* SPI/CS output (low-active) for serial flash */ -+ gpio_direction_output(22, 1); -+ -+ /* EBU.FL_CS1 as output for NAND CE */ -+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A23 as output for NAND CLE */ -+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A24 as output for NAND ALE */ -+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ -+ /* enable CLK_OUT2 for external switch */ -+ gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+} -+ -+int board_early_init_f(void) -+{ -+ gpio_init(); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Lantiq ADM6996I switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device adm6996i_dev = { -+ .name = "adm6996i", -+ .cpu_port = 5, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ /* Deactivate HRST line to release reset of ADM6996I switch */ -+ ltq_reset_once(LTQ_RESET_HARD, 200000); -+ -+ /* ADM6996I needs some time to come out of reset */ -+ __udelay(50000); -+ -+ return switch_device_register(&adm6996i_dev); -+} -+ -+int spi_cs_is_valid(unsigned int bus, unsigned int cs) -+{ -+ if (bus) -+ return 0; -+ -+ switch (cs) { -+ case 2: -+ return 1; -+ default: -+ return 0; -+ } -+} -+ -+void spi_cs_activate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 2: -+ gpio_set_value(22, 0); -+ break; -+ default: -+ break; -+ } -+} -+ -+void spi_cs_deactivate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 2: -+ gpio_set_value(22, 1); -+ break; -+ default: -+ break; -+ } -+} ---- /dev/null -+++ b/board/lantiq/easy80920/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/lantiq/easy80920/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/lantiq/easy80920/ddr_settings.h -@@ -0,0 +1,69 @@ -+/* -+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_CCR00_VALUE 0x101 -+#define MC_CCR01_VALUE 0x1000100 -+#define MC_CCR02_VALUE 0x1010000 -+#define MC_CCR03_VALUE 0x101 -+#define MC_CCR04_VALUE 0x1000000 -+#define MC_CCR05_VALUE 0x1000101 -+#define MC_CCR06_VALUE 0x1000100 -+#define MC_CCR07_VALUE 0x1010000 -+#define MC_CCR08_VALUE 0x1000101 -+#define MC_CCR09_VALUE 0x0 -+#define MC_CCR10_VALUE 0x2000100 -+#define MC_CCR11_VALUE 0x2000300 -+#define MC_CCR12_VALUE 0x30000 -+#define MC_CCR13_VALUE 0x202 -+#define MC_CCR14_VALUE 0x7080A0F -+#define MC_CCR15_VALUE 0x2040F -+#define MC_CCR16_VALUE 0x40000 -+#define MC_CCR17_VALUE 0x70102 -+#define MC_CCR18_VALUE 0x4020002 -+#define MC_CCR19_VALUE 0x30302 -+#define MC_CCR20_VALUE 0x8000700 -+#define MC_CCR21_VALUE 0x40F020A -+#define MC_CCR22_VALUE 0x0 -+#define MC_CCR23_VALUE 0xC020000 -+#define MC_CCR24_VALUE 0x4401B04 -+#define MC_CCR25_VALUE 0x0 -+#define MC_CCR26_VALUE 0x0 -+#define MC_CCR27_VALUE 0x6420000 -+#define MC_CCR28_VALUE 0x0 -+#define MC_CCR29_VALUE 0x0 -+#define MC_CCR30_VALUE 0x798 -+#define MC_CCR31_VALUE 0x0 -+#define MC_CCR32_VALUE 0x0 -+#define MC_CCR33_VALUE 0x650000 -+#define MC_CCR34_VALUE 0x200C8 -+#define MC_CCR35_VALUE 0x1D445D -+#define MC_CCR36_VALUE 0xC8 -+#define MC_CCR37_VALUE 0xC351 -+#define MC_CCR38_VALUE 0x0 -+#define MC_CCR39_VALUE 0x141F04 -+#define MC_CCR40_VALUE 0x142704 -+#define MC_CCR41_VALUE 0x141b42 -+#define MC_CCR42_VALUE 0x141b42 -+#define MC_CCR43_VALUE 0x566504 -+#define MC_CCR44_VALUE 0x566504 -+#define MC_CCR45_VALUE 0x565F17 -+#define MC_CCR46_VALUE 0x565F17 -+#define MC_CCR47_VALUE 0x0 -+#define MC_CCR48_VALUE 0x0 -+#define MC_CCR49_VALUE 0x0 -+#define MC_CCR50_VALUE 0x0 -+#define MC_CCR51_VALUE 0x0 -+#define MC_CCR52_VALUE 0x133 -+#define MC_CCR53_VALUE 0xF3014B27 -+#define MC_CCR54_VALUE 0xF3014B27 -+#define MC_CCR55_VALUE 0xF3014B27 -+#define MC_CCR56_VALUE 0xF3014B27 -+#define MC_CCR57_VALUE 0x7800301 -+#define MC_CCR58_VALUE 0x7800301 -+#define MC_CCR59_VALUE 0x7800301 -+#define MC_CCR60_VALUE 0x7800301 -+#define MC_CCR61_VALUE 0x4 ---- /dev/null -+++ b/board/lantiq/easy80920/easy80920.c -@@ -0,0 +1,138 @@ -+/* -+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_SPL_BUILD) -+#define do_gpio_init 1 -+#define do_pll_init 1 -+#define do_dcdc_init 0 -+#elif defined(CONFIG_SYS_BOOT_RAM) -+#define do_gpio_init 1 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#elif defined(CONFIG_SYS_BOOT_NOR) -+#define do_gpio_init 1 -+#define do_pll_init 1 -+#define do_dcdc_init 1 -+#else -+#define do_gpio_init 0 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#endif -+ -+static void gpio_init(void) -+{ -+ /* SPI CS 0.4 to serial flash */ -+ gpio_direction_output(10, 1); -+ -+ /* EBU.FL_CS1 as output for NAND CE */ -+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A23 as output for NAND CLE */ -+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A24 as output for NAND ALE */ -+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* GPIO 3.0 as input for NAND Ready Busy */ -+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); -+ /* GPIO 3.1 as output for NAND Read */ -+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+} -+ -+int board_early_init_f(void) -+{ -+ if (do_gpio_init) -+ gpio_init(); -+ -+ if (do_pll_init) -+ ltq_pll_init(); -+ -+ if (do_dcdc_init) -+ ltq_dcdc_init(0x7F); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ -+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ -+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ -+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, -+ /* GMAC3: unused */ -+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, -+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ -+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, -+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ -+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t * bis) -+{ -+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; -+ const ulong fw_addr = 0x80FF0000; -+ -+ ltq_gphy_phy11g_a1x_load(fw_addr); -+ -+ ltq_cgu_gphy_clk_src(clk); -+ -+ ltq_rcu_gphy_boot(0, fw_addr); -+ ltq_rcu_gphy_boot(1, fw_addr); -+ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+int spi_cs_is_valid(unsigned int bus, unsigned int cs) -+{ -+ if (bus) -+ return 0; -+ -+ if (cs == 4) -+ return 1; -+ -+ return 0; -+} -+ -+void spi_cs_activate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 0); -+ break; -+ default: -+ break; -+ } -+} -+ -+void spi_cs_deactivate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 1); -+ break; -+ default: -+ break; -+ } -+} ---- a/boards.cfg -+++ b/boards.cfg -@@ -502,10 +502,17 @@ Active mips mips32 au1x0 - Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange - Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange - Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - -+Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck -+Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck -+Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck - Active mips mips32 incaip - incaip incaip - Wolfgang Denk - Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk -+Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck -+Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck -+Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck -+Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck - Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - - Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - - Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -12,6 +12,7 @@ LIB := $(obj)libdma.o @@ -8782,183 +8297,6 @@ Signed-off-by: Daniel Schwierzeck + + return ret; +} ---- /dev/null -+++ b/include/configs/easy50712.h -@@ -0,0 +1,79 @@ -+/* -+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "EASY50712" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Lantiq EASY50712 Danube Reference Board" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+#define CONFIG_LTQ_SUPPORT_SPI_FLASH -+#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */ -+ -+#define CONFIG_LTQ_SUPPORT_NAND_FLASH -+ -+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ -+ -+#define CONFIG_LTQ_SPL_COMP_LZO -+#define CONFIG_LTQ_SPL_CONSOLE -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_ADM6996I -+ -+/* Environment */ -+#define CONFIG_ENV_SPI_BUS 0 -+#define CONFIG_ENV_SPI_CS 2 -+#define CONFIG_ENV_SPI_MAX_HZ 20000000 -+#define CONFIG_ENV_SPI_MODE 0 -+ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#elif defined(CONFIG_SYS_BOOT_NORSPL) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (128 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+ -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Commands */ -+#define CONFIG_CMD_PING -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR -+ -+#endif /* __CONFIG_H */ ---- /dev/null -+++ b/include/configs/easy80920.h -@@ -0,0 +1,92 @@ -+/* -+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "EASY80920" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Lantiq EASY80920 VRX200 Family Board" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+#define CONFIG_LTQ_SUPPORT_SPI_FLASH -+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */ -+ -+#define CONFIG_LTQ_SUPPORT_NAND_FLASH -+ -+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ -+#define CONFIG_SPL_SPI_BUS 0 -+#define CONFIG_SPL_SPI_CS 4 -+#define CONFIG_SPL_SPI_MAX_HZ 25000000 -+#define CONFIG_SPL_SPI_MODE 0 -+ -+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ -+ -+#define CONFIG_LTQ_SPL_COMP_LZO -+#define CONFIG_LTQ_SPL_CONSOLE -+ -+#define CONFIG_SYS_DRAM_PROBE -+ -+/* Environment */ -+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS -+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS -+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ -+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE -+ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (384 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#elif defined(CONFIG_SYS_BOOT_NORSPL) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#elif defined(CONFIG_SYS_BOOT_SFSPL) -+#define CONFIG_ENV_IS_IN_SPI_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+ -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Commands */ -+#define CONFIG_CMD_PING -+ -+/* Pull in default board configs for Lantiq XWAY VRX200 */ -+#include -+#include -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_SF \ -+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ CONFIG_ENV_UPDATE_UBOOT_SF -+ -+#endif /* __CONFIG_H */ --- a/include/phy.h +++ b/include/phy.h @@ -214,6 +214,7 @@ int phy_atheros_init(void); diff --git a/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-add-default-openwrt-config.patch b/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-add-default-openwrt-config.patch new file mode 100644 index 0000000000..3b50c981c9 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-add-default-openwrt-config.patch @@ -0,0 +1,50 @@ +From 8f584936adad0fca8beece5f55eadcdcd02fad0a Mon Sep 17 00:00:00 2001 +From: Luka Perkov +Date: Sat, 17 Aug 2013 03:44:46 +0200 +Subject: MIPS: lantiq: add default openwrt config + +Signed-off-by: Luka Perkov +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/include/configs/openwrt-lantiq-common.h +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __OPENWRT_LANTIQ_COMMON_H ++#define __OPENWRT_LANTIQ_COMMON_H ++ ++/* Commands */ ++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) ++#define CONFIG_CMD_PING ++#endif ++ ++/* Compression */ ++#define CONFIG_LZMA ++ ++/* Auto boot */ ++#define CONFIG_BOOTDELAY 2 ++ ++/* Environment */ ++#if !defined(CONFIG_SYS_BOOT_RAM) ++#define CONFIG_BOOTCOMMAND \ ++ "bootm ${kernel_addr}" ++#endif ++ ++/* Ethernet */ ++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) ++#define CONFIG_ETHADDR 00:01:02:03:04:05 ++#define CONFIG_SERVERIP 192.168.1.2 ++#define CONFIG_IPADDR 192.168.1.1 ++#endif ++ ++/* Unnecessary */ ++#undef CONFIG_BOOTM_NETBSD ++#undef CONFIG_BOOTM_PLAN9 ++#undef CONFIG_BOOTM_RTEMS ++ ++#endif /* __OPENWRT_LANTIQ_COMMON_H */ diff --git a/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch b/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch deleted file mode 100644 index 8e1d5bd913..0000000000 --- a/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 6fa1c350fa19a054371eccef84e4885cfdd6a2d7 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck -Date: Mon, 19 Aug 2013 18:11:31 +0200 -Subject: MIPS: lantiq: easy80920: add support for NAND SPL - -Signed-off-by: Daniel Schwierzeck - ---- a/boards.cfg -+++ b/boards.cfg -@@ -509,6 +509,7 @@ Active mips mips32 incai - Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk -+Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck ---- a/include/configs/easy80920.h -+++ b/include/configs/easy80920.h -@@ -31,6 +31,14 @@ - - #define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ - -+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ -+#define CONFIG_SYS_NAND_PAGE_COUNT 128 -+#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -+#define CONFIG_SYS_NAND_OOBSIZE 64 -+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) -+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 -+ - #define CONFIG_LTQ_SPL_COMP_LZO - #define CONFIG_LTQ_SPL_CONSOLE - -@@ -57,6 +65,11 @@ - #define CONFIG_ENV_OVERWRITE - #define CONFIG_ENV_OFFSET (192 * 1024) - #define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#elif defined(CONFIG_SYS_BOOT_NANDSPL) -+#define CONFIG_ENV_IS_IN_NAND -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SECT_SIZE (256 * 1024) - #else - #define CONFIG_ENV_IS_NOWHERE - #endif -@@ -84,9 +97,13 @@ - #define CONFIG_ENV_UPDATE_UBOOT_SF \ - "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" - -+#define CONFIG_ENV_UPDATE_UBOOT_NAND \ -+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" -+ - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_ENV_LANTIQ_DEFAULTS \ - CONFIG_ENV_UPDATE_UBOOT_NOR \ -- CONFIG_ENV_UPDATE_UBOOT_SF -+ CONFIG_ENV_UPDATE_UBOOT_SF \ -+ CONFIG_ENV_UPDATE_UBOOT_NAND - - #endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch b/package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch deleted file mode 100644 index 3b50c981c9..0000000000 --- a/package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 8f584936adad0fca8beece5f55eadcdcd02fad0a Mon Sep 17 00:00:00 2001 -From: Luka Perkov -Date: Sat, 17 Aug 2013 03:44:46 +0200 -Subject: MIPS: lantiq: add default openwrt config - -Signed-off-by: Luka Perkov -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/include/configs/openwrt-lantiq-common.h -@@ -0,0 +1,39 @@ -+/* -+ * Copyright (C) 2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __OPENWRT_LANTIQ_COMMON_H -+#define __OPENWRT_LANTIQ_COMMON_H -+ -+/* Commands */ -+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) -+#define CONFIG_CMD_PING -+#endif -+ -+/* Compression */ -+#define CONFIG_LZMA -+ -+/* Auto boot */ -+#define CONFIG_BOOTDELAY 2 -+ -+/* Environment */ -+#if !defined(CONFIG_SYS_BOOT_RAM) -+#define CONFIG_BOOTCOMMAND \ -+ "bootm ${kernel_addr}" -+#endif -+ -+/* Ethernet */ -+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) -+#define CONFIG_ETHADDR 00:01:02:03:04:05 -+#define CONFIG_SERVERIP 192.168.1.2 -+#define CONFIG_IPADDR 192.168.1.1 -+#endif -+ -+/* Unnecessary */ -+#undef CONFIG_BOOTM_NETBSD -+#undef CONFIG_BOOTM_PLAN9 -+#undef CONFIG_BOOTM_RTEMS -+ -+#endif /* __OPENWRT_LANTIQ_COMMON_H */ diff --git a/package/boot/uboot-lantiq/patches/0023-lzma-fixup.patch b/package/boot/uboot-lantiq/patches/0023-lzma-fixup.patch new file mode 100644 index 0000000000..7c15938330 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0023-lzma-fixup.patch @@ -0,0 +1,39 @@ +From: Antonios Vamporakis +Date: Tue, 31 Dec 2013 01:05:42 +0100 +Subject: [PATCH] lzma: fix buffer bound check error + +Variable uncompressedSize references the space available, while outSizeFull is +the actual expected uncompressed size. Using the wrong value causes LzmaDecode +to return SZ_ERROR_INPUT_EOF. Problem was introduced in commit afca294. While +at it add additional debug message. + +Signed-off-by: Antonios Vamporakis +CC: Kees Cook +CC: Simon Glass +CC: Daniel Schwierzeck +CC: Luka Perkov +--- + lib/lzma/LzmaTools.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/lib/lzma/LzmaTools.c ++++ b/lib/lzma/LzmaTools.c +@@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned c + return SZ_ERROR_OUTPUT_EOF; + + /* Decompress */ +- outProcessed = *uncompressedSize; ++ outProcessed = outSizeFull; + + WATCHDOG_RESET(); + +@@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned c + inStream + LZMA_DATA_OFFSET, &compressedSize, + inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc); + *uncompressedSize = outProcessed; ++ ++ debug("LZMA: Uncompresed ................ 0x%zx\n", outProcessed); ++ + if (res != SZ_OK) { + return res; + } diff --git a/package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch b/package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch deleted file mode 100644 index 5afe42796d..0000000000 --- a/package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch +++ /dev/null @@ -1,26 +0,0 @@ -From ac6896098d9dd62a248340e6a090574399e1fd87 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck -Date: Mon, 19 Aug 2013 18:46:47 +0200 -Subject: MIPS: lantiq: easy50712: add openwrt-lantiq-common.h - -Signed-off-by: Daniel Schwierzeck - ---- a/include/configs/easy50712.h -+++ b/include/configs/easy50712.h -@@ -62,13 +62,13 @@ - #define CONFIG_CONSOLE_ASC 1 - #define CONFIG_CONSOLE_DEV "ttyLTQ1" - --/* Commands */ --#define CONFIG_CMD_PING -- - /* Pull in default board configs for Lantiq XWAY Danube */ - #include - #include - -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ - #define CONFIG_ENV_UPDATE_UBOOT_NOR \ - "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" - diff --git a/package/boot/uboot-lantiq/patches/0024-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch b/package/boot/uboot-lantiq/patches/0024-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch new file mode 100644 index 0000000000..1f89e54608 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0024-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch @@ -0,0 +1,18 @@ +From 7e2f79bc40b572763a4a1ed69f63aa2eaa6df254 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck +Date: Sun, 20 Oct 2013 19:39:17 +0200 +Subject: Makefile: prepare u-boot-lantiq-v2013.10-openwrt4 + +Signed-off-by: Daniel Schwierzeck + +--- a/Makefile ++++ b/Makefile +@@ -8,7 +8,7 @@ + VERSION = 2013 + PATCHLEVEL = 10 + SUBLEVEL = +-EXTRAVERSION = ++EXTRAVERSION = -openwrt4 + ifneq "$(SUBLEVEL)" "" + U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) + else diff --git a/package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch b/package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch deleted file mode 100644 index 2f9fd59d38..0000000000 --- a/package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 7afbe4633773905ef94a8404510fb5a459926000 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck -Date: Mon, 19 Aug 2013 18:11:57 +0200 -Subject: MIPS: lantiq: easy80920: add openwrt-lantiq-common.h - -Signed-off-by: Daniel Schwierzeck - ---- a/include/configs/easy80920.h -+++ b/include/configs/easy80920.h -@@ -84,13 +84,13 @@ - #define CONFIG_CONSOLE_ASC 1 - #define CONFIG_CONSOLE_DEV "ttyLTQ1" - --/* Commands */ --#define CONFIG_CMD_PING -- - /* Pull in default board configs for Lantiq XWAY VRX200 */ - #include - #include - -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ - #define CONFIG_ENV_UPDATE_UBOOT_NOR \ - "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" - diff --git a/package/boot/uboot-lantiq/patches/0025-arx100-cgu-fixes.patch b/package/boot/uboot-lantiq/patches/0025-arx100-cgu-fixes.patch new file mode 100644 index 0000000000..ff2f99c08d --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0025-arx100-cgu-fixes.patch @@ -0,0 +1,148 @@ +From patchwork Tue Jan 20 11:28:45 2015 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image +From: Ben Mulvihill +X-Patchwork-Id: 431024 +Message-Id: <1421753325.25187.58.camel@merveille.lan> +To: Daniel Schwierzeck +Cc: OpenWrt Development List +Date: Tue, 20 Jan 2015 12:28:45 +0100 + +On Tue, 2015-01-20 at 00:39 +0100, Ben Mulvihill wrote: +> On Mon, 2015-01-19 at 19:21 +0100, Ben Mulvihill wrote: +> > On Mon, 2015-01-19 at 16:47 +0100, Daniel Schwierzeck wrote: +> > > 2015-01-19 15:44 GMT+01:00 Ben Mulvihill : +> > > > On Mon, 2015-01-19 at 11:51 +0000, Conor O'Gorman wrote: +> > > >> On 19/01/15 10:46, Ben Mulvihill wrote: +> > > >> > Hello, +> > > >> > +> > > >> > I am trying to build uboot-lantiq for the BT Home Hub 3A (lantiq +> > > >> > ar9), and am wondering where to initialise the cgu, in the case +> > > >> > of a ramboot image for uart booting. Normally the cgu is initialised +> > > >> > in lowlevel_init, but that code is bypassed in ramboot images. The +> > > >> > result is that the board boots with the wrong cgu settings, which +> > > >> > sends the console haywire. So far I have tried two solutions: +> > > >> +> > > >> Another option is to try and not change anything. The console is already +> > > >> configured and running. The ram does need config. +> > > >> +> > > >> I was used to seeing the ramboot version running at half clock speed, at +> > > >> least on danube, previous to ar9. +> > > >> +> > > >> Conor +> > > > +> > > > Hi Conor, +> > > > +> > > > Thanks for the reply. But with the latest uboot-lantiq, not changing +> > > > anything means that I don't get a usable console. With an older +> > > > version I do at least get a uboot console, but no linux console when +> > > > I boot openwrt. Correcting the cgu settings solves both problems. +> > > > +> > > +> > > could you try this? +> > > +> > > diff --git a/arch/mips/cpu/mips32/arx100/cgu.c +> > > b/arch/mips/cpu/mips32/arx100/cgu.c +> > > index 6e71ee7..e0afbda 100644 +> > > --- a/arch/mips/cpu/mips32/arx100/cgu.c +> > > +++ b/arch/mips/cpu/mips32/arx100/cgu.c +> > > @@ -95,15 +95,5 @@ unsigned long ltq_get_cpu_clock(void) +> > > +> > > unsigned long ltq_get_bus_clock(void) +> > > { +> > > - u32 fpi_sel; +> > > - unsigned long clk; +> > > - +> > > - fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL); +> > > - +> > > - if (fpi_sel) +> > > - clk = ltq_get_io_region_clock() / 2; +> > > - else +> > > - clk = ltq_get_io_region_clock(); +> > > - +> > > - return clk; +> > > + return ltq_get_io_region_clock(); +> > > } +> > > +> > > the UART driver calculates the baudrate from the FPI bus clock, but +> > > FPI_SEL is not available on AR9. FPI bus clock is always the same as +> > > DDR clock, Obviously a copy&paste error from VR9 code ;) +> > > +> > +> > No, even with this patch, I still don't get a working console I'm +> > afraid. If I don't set anything explicitly, the board comes up with +> > CGU_SYS set to 0x05, ie CGU_SYS_SYSSEL_PLL0_333_MHZ | +> > CGU_SYS_CPUSEL_EQUAL_DDRCLK | CGU_SYS_DDRSEL_THIRD_SYSCLK. +> > Is this a valid combination without CGU_SYS_PPESEL_250_MHZ ? +> > I don't understand what CGU_SYS_PPESEL_250_MHZ does? +> > The "right setting", as set by the stock uboot, is 0x80. +> +> P.S. There also seems to be a discrepancy between the uboot and +> linux code. I take it from what you say above that fpi clock, ddr +> clock and io region clock are all the same. Now if the least +> significant bit of CGU_SYS is set, then according to the uboot +> code - function ltq_get_bus_clock() - their value is one +> third of the system clock. But according to the linux code +> - function ltq_ar9_fpi_hz() in arch/mips/lantiq/xway/clk.c - +> their value in this case is equal to the system clock. +> +> Or am I getting muddled? It's past my bedtime! +> +> + +Some of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1 +out. A patch along these lines should fix it: + +--- a/arch/mips/cpu/mips32/arx100/cgu.c ++++ b/arch/mips/cpu/mips32/arx100/cgu.c +@@ -10,12 +10,17 @@ + #include + #include + +-#define CGU_SYS_DDR_SEL (1 << 0) +-#define CGU_SYS_CPU_SEL (1 << 2) ++#define CGU_SYS_DDR_SHIFT 0 ++#define CGU_SYS_CPU_SHIFT 2 + #define CGU_SYS_SYS_SHIFT 3 ++#define CGU_SYS_FPI_SHIFT 6 ++#define CGU_SYS_PPE_SHIFT 7 ++ ++#define CGU_SYS_DDR_MASK (1 << CGU_SYS_DDR_SHIFT) ++#define CGU_SYS_CPU_MASK (1 << CGU_SYS_CPU_SHIFT) + #define CGU_SYS_SYS_MASK (0x3 << CGU_SYS_SYS_SHIFT) +-#define CGU_SYS_FPI_SEL (1 << 6) +-#define CGU_SYS_PPE_SEL (1 << 7) ++#define CGU_SYS_FPI_MASK (1 << CGU_SYS_FPI_SHIFT) ++#define CGU_SYS_PPE_MASK (1 << CGU_SYS_PPE_SHIFT) + + struct ltq_cgu_regs { + u32 rsvd0; +@@ -68,7 +73,7 @@ unsigned long ltq_get_io_region_clock(vo + u32 ddr_sel; + unsigned long clk; + +- ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL); ++ ddr_sel = ltq_cgu_sys_readl(CGU_SYS_DDR_MASK, CGU_SYS_DDR_SHIFT); + + if (ddr_sel) + clk = ltq_get_system_clock() / 3; +@@ -83,7 +88,7 @@ unsigned long ltq_get_cpu_clock(void) + u32 cpu_sel; + unsigned long clk; + +- cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL); ++ cpu_sel = ltq_cgu_sys_readl(CGU_SYS_CPU_MASK, CGU_SYS_CPU_SHIFT); + + if (cpu_sel) + clk = ltq_get_io_region_clock(); +@@ -98,7 +103,7 @@ unsigned long ltq_get_bus_clock(void) + u32 fpi_sel; + unsigned long clk; + +- fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL); ++ fpi_sel = ltq_cgu_sys_readl(CGU_SYS_FPI_MASK, CGU_SYS_FPI_SHIFT); + + if (fpi_sel) + clk = ltq_get_io_region_clock() / 2; diff --git a/package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch b/package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch deleted file mode 100644 index 51738e40b8..0000000000 --- a/package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 9f915cf9550a6234adecaf3031c2b279835e14af Mon Sep 17 00:00:00 2001 -From: Luka Perkov -Date: Sat, 2 Mar 2013 23:34:00 +0100 -Subject: MIPS: add board support for Arcadyan ARV4519 - -Signed-off-by: Luka Perkov -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/board/arcadyan/arv4519pw/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/arcadyan/arv4519pw/arv4519pw.c -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (C) 2012 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_early_init_f(void) -+{ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Atheros ar8216 switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device ar8216_dev = { -+ .name = "ar8216", -+ .cpu_port = 0, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ return switch_device_register(&ar8216_dev); -+} ---- /dev/null -+++ b/board/arcadyan/arv4519pw/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/arcadyan/arv4519pw/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2012-2013 Luka Perkov -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x131 -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x301 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA04 -+#define MC_DC21_VALUE 0x1700 -+#define MC_DC22_VALUE 0x1717 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x5A -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x4E20 -+#define MC_DC30_VALUE 0x8235 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- a/boards.cfg -+++ b/boards.cfg -@@ -502,6 +502,9 @@ Active mips mips32 au1x0 - Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange - Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange - Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - -+Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov -+Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov -+Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov - Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck ---- /dev/null -+++ b/include/configs/arv4519pw.h -@@ -0,0 +1,67 @@ -+/* -+ * Copyright (C) 2012-2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ARV4519PW" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Arcadyan ARV4519PW" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_AR8216 -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Brnboot loadable image */ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_OVERWRITE 1 -+#endif -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0040000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0026-no_extern_inline.patch b/package/boot/uboot-lantiq/patches/0026-no_extern_inline.patch new file mode 100644 index 0000000000..70216f2e78 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0026-no_extern_inline.patch @@ -0,0 +1,97 @@ +From b11c5d1dc29e81326d1215011d19377737082aeb Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck +Date: Wed, 1 Jul 2015 16:36:43 +0200 +Subject: [PATCH] MIPS: change 'extern inline' to 'static inline' + +The kernel changed it a long time ago. Also this is now broken +on gcc-5.x. + +Reported-by: Andy Kennedy +Signed-off-by: Daniel Schwierzeck +--- + arch/mips/include/asm/io.h | 12 ++++++------ + arch/mips/include/asm/system.h | 6 +++--- + 2 files changed, 9 insertions(+), 9 deletions(-) + +--- a/arch/mips/include/asm/io.h ++++ b/arch/mips/include/asm/io.h +@@ -118,7 +118,7 @@ static inline void set_io_port_base(unsi + * Change virtual addresses to physical addresses and vv. + * These are trivial on the 1:1 Linux/MIPS mapping + */ +-extern inline phys_addr_t virt_to_phys(volatile void * address) ++static inline phys_addr_t virt_to_phys(volatile void * address) + { + #ifndef CONFIG_64BIT + return CPHYSADDR(address); +@@ -127,7 +127,7 @@ extern inline phys_addr_t virt_to_phys(v + #endif + } + +-extern inline void * phys_to_virt(unsigned long address) ++static inline void * phys_to_virt(unsigned long address) + { + #ifndef CONFIG_64BIT + return (void *)KSEG0ADDR(address); +@@ -139,7 +139,7 @@ extern inline void * phys_to_virt(unsign + /* + * IO bus memory addresses are also 1:1 with the physical address + */ +-extern inline unsigned long virt_to_bus(volatile void * address) ++static inline unsigned long virt_to_bus(volatile void * address) + { + #ifndef CONFIG_64BIT + return CPHYSADDR(address); +@@ -148,7 +148,7 @@ extern inline unsigned long virt_to_bus( + #endif + } + +-extern inline void * bus_to_virt(unsigned long address) ++static inline void * bus_to_virt(unsigned long address) + { + #ifndef CONFIG_64BIT + return (void *)KSEG0ADDR(address); +@@ -166,12 +166,12 @@ extern unsigned long isa_slot_offset; + extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); + + #if 0 +-extern inline void *ioremap(unsigned long offset, unsigned long size) ++static inline void *ioremap(unsigned long offset, unsigned long size) + { + return __ioremap(offset, size, _CACHE_UNCACHED); + } + +-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) ++static inline void *ioremap_nocache(unsigned long offset, unsigned long size) + { + return __ioremap(offset, size, _CACHE_UNCACHED); + } +--- a/arch/mips/include/asm/system.h ++++ b/arch/mips/include/asm/system.h +@@ -23,7 +23,7 @@ + #include + #endif + +-extern __inline__ void ++static __inline__ void + __sti(void) + { + __asm__ __volatile__( +@@ -47,7 +47,7 @@ __sti(void) + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs + * no nops at all. + */ +-extern __inline__ void ++static __inline__ void + __cli(void) + { + __asm__ __volatile__( +@@ -208,7 +208,7 @@ do { \ + * For 32 and 64 bit operands we can take advantage of ll and sc. + * FIXME: This doesn't work for R3000 machines. + */ +-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) ++static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) + { + #ifdef CONFIG_CPU_HAS_LLSC + unsigned long dummy; diff --git a/package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch b/package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch deleted file mode 100644 index 21e6a2c5e9..0000000000 --- a/package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 54a31b334162e8dc2ea891057ddeab42978db8b3 Mon Sep 17 00:00:00 2001 -From: Luka Perkov -Date: Sat, 2 Mar 2013 23:34:00 +0100 -Subject: MIPS: add board support for Arcadyan ARV7518 - -Signed-off-by: Luka Perkov -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/board/arcadyan/arv7518pw/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/arcadyan/arv7518pw/arv7518pw.c -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (C) 2012 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_early_init_f(void) -+{ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Atheros ar8216 switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device ar8216_dev = { -+ .name = "ar8216", -+ .cpu_port = 0, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ return switch_device_register(&ar8216_dev); -+} ---- /dev/null -+++ b/board/arcadyan/arv7518pw/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/arcadyan/arv7518pw/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2012-2013 Luka Perkov -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x134 -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x301 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA03 -+#define MC_DC21_VALUE 0x1400 -+#define MC_DC22_VALUE 0x1414 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x5B -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x4E20 -+#define MC_DC30_VALUE 0x8235 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- a/boards.cfg -+++ b/boards.cfg -@@ -505,6 +505,9 @@ Active mips mips32 au1x0 - Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov - Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov - Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov -+Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov -+Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov -+Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov - Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck ---- /dev/null -+++ b/include/configs/arv7518pw.h -@@ -0,0 +1,67 @@ -+/* -+ * Copyright (C) 2012-2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ARV7518PW" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Arcadyan ARV7518PW" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_AR8216 -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Brnboot loadable image */ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_OVERWRITE 1 -+#endif -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0040000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0027-no_weak_alias.patch b/package/boot/uboot-lantiq/patches/0027-no_weak_alias.patch new file mode 100644 index 0000000000..da519a5f1d --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0027-no_weak_alias.patch @@ -0,0 +1,26 @@ +From 3422299dc28fa8257677d03cc1253e3c9bf17e9f Mon Sep 17 00:00:00 2001 +From: Jeroen Hofstee +Date: Thu, 26 Jun 2014 20:18:31 +0200 +Subject: [PATCH] common: main.c: make show_boot_progress __weak + +This not only looks a bit better it also prevents a +warning with W=1 (no previous prototype). + +Signed-off-by: Jeroen Hofstee +Acked-by: Simon Glass +--- + common/main.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/common/main.c ++++ b/common/main.c +@@ -27,8 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; + /* + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ +-void inline __show_boot_progress (int val) {} +-void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); ++__weak void show_boot_progress(int val) {} + + #define MAX_DELAY_STOP_STR 32 + diff --git a/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch b/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch deleted file mode 100644 index 00820f8e3d..0000000000 --- a/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch +++ /dev/null @@ -1,248 +0,0 @@ -From 4bacfc80eae768be45f9ddf7588ec55281354648 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 8 Mar 2013 13:29:04 +0200 -Subject: MIPS: add board support for AudioCodes MP-252 - -Signed-off-by: Daniel Golle - ---- /dev/null -+++ b/board/audiocodes/acmp252/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/audiocodes/acmp252/acmp252.c -@@ -0,0 +1,66 @@ -+/* -+ * Copyright (C) 2013 Daniel Golle -+ * Copyright (C) 2011 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static void gpio_init(void) -+{ -+ /* Activate reset line of ADM6996I switch */ -+ gpio_direction_output(19, 0); -+} -+ -+int board_early_init_f(void) -+{ -+ gpio_init(); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Lantiq ADM6996I switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device adm6996i_dev = { -+ .name = "adm6996i", -+ .cpu_port = 5, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ /* Deactivate reset line of ADM6996I switch */ -+ gpio_set_value(19, 1); -+ -+ /* ADM6996I needs some time to come out of reset */ -+ __udelay(50000); -+ -+ return switch_device_register(&adm6996i_dev); -+} ---- /dev/null -+++ b/board/audiocodes/acmp252/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/audiocodes/acmp252/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2011-2013 Luka Perkov -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x403 -+#define MC_DC08_VALUE 0x103 -+#define MC_DC09_VALUE 0x80B -+#define MC_DC10_VALUE 0x304 -+#define MC_DC11_VALUE 0xD03 -+#define MC_DC12_VALUE 0x2C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x13C -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x402 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA03 -+#define MC_DC21_VALUE 0x1700 -+#define MC_DC22_VALUE 0x1717 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x5C -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x2D93 -+#define MC_DC30_VALUE 0x8300 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- a/boards.cfg -+++ b/boards.cfg -@@ -508,6 +508,8 @@ Active mips mips32 danub - Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov -+Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle -+Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle - Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck ---- /dev/null -+++ b/include/configs/acmp252.h -@@ -0,0 +1,60 @@ -+/* -+ * Copyright (C) 2013 Daniel Golle -+ * Copyright (C) 2011 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ACMP252" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "AudioCodes MP-252" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_ADM6996I -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SECT_SIZE (128 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0040000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0028-add-gcc5-support.patch b/package/boot/uboot-lantiq/patches/0028-add-gcc5-support.patch new file mode 100644 index 0000000000..3ae76a7ff6 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0028-add-gcc5-support.patch @@ -0,0 +1,87 @@ +From 478b02f1a7043b673565075ea5016376f3293b23 Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Sat, 7 Feb 2015 22:52:40 +0100 +Subject: [PATCH] Add linux/compiler-gcc5.h to fix builds with gcc5 + +Add linux/compiler-gcc5/h from the kernel sources at: + +commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b +Author: Steven Noonan +Date: Sat Oct 25 15:09:42 2014 -0700 + + compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles + +Signed-off-by: Hans de Goede +--- + include/linux/compiler-gcc5.h | 65 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 65 insertions(+) + create mode 100644 include/linux/compiler-gcc5.h + +--- /dev/null ++++ b/include/linux/compiler-gcc5.h +@@ -0,0 +1,65 @@ ++#ifndef __LINUX_COMPILER_H ++#error "Please don't include directly, include instead." ++#endif ++ ++#define __used __attribute__((__used__)) ++#define __must_check __attribute__((warn_unused_result)) ++#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) ++ ++/* Mark functions as cold. gcc will assume any path leading to a call ++ to them will be unlikely. This means a lot of manual unlikely()s ++ are unnecessary now for any paths leading to the usual suspects ++ like BUG(), printk(), panic() etc. [but let's keep them for now for ++ older compilers] ++ ++ Early snapshots of gcc 4.3 don't support this and we can't detect this ++ in the preprocessor, but we can live with this because they're unreleased. ++ Maketime probing would be overkill here. ++ ++ gcc also has a __attribute__((__hot__)) to move hot functions into ++ a special section, but I don't see any sense in this right now in ++ the kernel context */ ++#define __cold __attribute__((__cold__)) ++ ++#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) ++ ++#ifndef __CHECKER__ ++# define __compiletime_warning(message) __attribute__((warning(message))) ++# define __compiletime_error(message) __attribute__((error(message))) ++#endif /* __CHECKER__ */ ++ ++/* ++ * Mark a position in code as unreachable. This can be used to ++ * suppress control flow warnings after asm blocks that transfer ++ * control elsewhere. ++ * ++ * Early snapshots of gcc 4.5 don't support this and we can't detect ++ * this in the preprocessor, but we can live with this because they're ++ * unreleased. Really, we need to have autoconf for the kernel. ++ */ ++#define unreachable() __builtin_unreachable() ++ ++/* Mark a function definition as prohibited from being cloned. */ ++#define __noclone __attribute__((__noclone__)) ++ ++/* ++ * Tell the optimizer that something else uses this function or variable. ++ */ ++#define __visible __attribute__((externally_visible)) ++ ++/* ++ * GCC 'asm goto' miscompiles certain code sequences: ++ * ++ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 ++ * ++ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. ++ * ++ * (asm goto is automatically volatile - the naming reflects this.) ++ */ ++#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) ++ ++#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP ++#define __HAVE_BUILTIN_BSWAP32__ ++#define __HAVE_BUILTIN_BSWAP64__ ++#define __HAVE_BUILTIN_BSWAP16__ ++#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch b/package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch deleted file mode 100644 index 77014e44ce..0000000000 --- a/package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch +++ /dev/null @@ -1,354 +0,0 @@ -From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck -Date: Sat, 2 Mar 2013 23:34:00 +0100 -Subject: MIPS: add board support for AVM FritzBox 3370 - -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/board/avm/fb3370/Makefile -@@ -0,0 +1,28 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/avm/fb3370/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/avm/fb3370/ddr_settings.h -@@ -0,0 +1,69 @@ -+/* -+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_CCR00_VALUE 0x101 -+#define MC_CCR01_VALUE 0x1000100 -+#define MC_CCR02_VALUE 0x1010000 -+#define MC_CCR03_VALUE 0x101 -+#define MC_CCR04_VALUE 0x1000000 -+#define MC_CCR05_VALUE 0x1000101 -+#define MC_CCR06_VALUE 0x1000100 -+#define MC_CCR07_VALUE 0x1010000 -+#define MC_CCR08_VALUE 0x1000101 -+#define MC_CCR09_VALUE 0x0 -+#define MC_CCR10_VALUE 0x2000100 -+#define MC_CCR11_VALUE 0x2000300 -+#define MC_CCR12_VALUE 0x30000 -+#define MC_CCR13_VALUE 0x202 -+#define MC_CCR14_VALUE 0x7080A0F -+#define MC_CCR15_VALUE 0x2040F -+#define MC_CCR16_VALUE 0x40000 -+#define MC_CCR17_VALUE 0x70102 -+#define MC_CCR18_VALUE 0x4020002 -+#define MC_CCR19_VALUE 0x30302 -+#define MC_CCR20_VALUE 0x8000700 -+#define MC_CCR21_VALUE 0x40F020A -+#define MC_CCR22_VALUE 0x0 -+#define MC_CCR23_VALUE 0xC020000 -+#define MC_CCR24_VALUE 0x4401B04 -+#define MC_CCR25_VALUE 0x0 -+#define MC_CCR26_VALUE 0x0 -+#define MC_CCR27_VALUE 0x6420000 -+#define MC_CCR28_VALUE 0x0 -+#define MC_CCR29_VALUE 0x0 -+#define MC_CCR30_VALUE 0x798 -+#define MC_CCR31_VALUE 0x0 -+#define MC_CCR32_VALUE 0x0 -+#define MC_CCR33_VALUE 0x650000 -+#define MC_CCR34_VALUE 0x200C8 -+#define MC_CCR35_VALUE 0x1D445D -+#define MC_CCR36_VALUE 0xC8 -+#define MC_CCR37_VALUE 0xC351 -+#define MC_CCR38_VALUE 0x0 -+#define MC_CCR39_VALUE 0x141F04 -+#define MC_CCR40_VALUE 0x142704 -+#define MC_CCR41_VALUE 0x141B42 -+#define MC_CCR42_VALUE 0x141B42 -+#define MC_CCR43_VALUE 0x566504 -+#define MC_CCR44_VALUE 0x566504 -+#define MC_CCR45_VALUE 0x565F17 -+#define MC_CCR46_VALUE 0x565F17 -+#define MC_CCR47_VALUE 0x0 -+#define MC_CCR48_VALUE 0x0 -+#define MC_CCR49_VALUE 0x0 -+#define MC_CCR50_VALUE 0x0 -+#define MC_CCR51_VALUE 0x0 -+#define MC_CCR52_VALUE 0x133 -+#define MC_CCR53_VALUE 0xF3014B27 -+#define MC_CCR54_VALUE 0xF3014B27 -+#define MC_CCR55_VALUE 0xF3014B27 -+#define MC_CCR56_VALUE 0xF3014B27 -+#define MC_CCR57_VALUE 0x7800301 -+#define MC_CCR58_VALUE 0x7800301 -+#define MC_CCR59_VALUE 0x7800301 -+#define MC_CCR60_VALUE 0x7800301 -+#define MC_CCR61_VALUE 0x4 ---- /dev/null -+++ b/board/avm/fb3370/fb3370.c -@@ -0,0 +1,138 @@ -+/* -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_SPL_BUILD) -+#define do_gpio_init 1 -+#define do_pll_init 1 -+#define do_dcdc_init 0 -+#elif defined(CONFIG_SYS_BOOT_RAM) -+#define do_gpio_init 1 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#elif defined(CONFIG_SYS_BOOT_NOR) -+#define do_gpio_init 1 -+#define do_pll_init 1 -+#define do_dcdc_init 1 -+#else -+#define do_gpio_init 0 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#endif -+ -+static void gpio_init(void) -+{ -+ /* SPI CS 0.4 to serial flash */ -+ gpio_direction_output(10, 1); -+ -+ /* EBU.FL_CS1 as output for NAND CE */ -+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A23 as output for NAND CLE */ -+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A24 as output for NAND ALE */ -+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* GPIO 3.0 as input for NAND Ready Busy */ -+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); -+ /* GPIO 3.1 as output for NAND Read */ -+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+} -+ -+int board_early_init_f(void) -+{ -+ if (do_gpio_init) -+ gpio_init(); -+ -+ if (do_pll_init) -+ ltq_pll_init(); -+ -+ if (do_dcdc_init) -+ ltq_dcdc_init(0x7F); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ -+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ -+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ -+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, -+ /* GMAC3: unused */ -+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, -+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ -+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, -+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ -+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t * bis) -+{ -+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; -+ const ulong fw_addr = 0x80FF0000; -+ -+ ltq_gphy_phy11g_a1x_load(fw_addr); -+ -+ ltq_cgu_gphy_clk_src(clk); -+ -+ ltq_rcu_gphy_boot(0, fw_addr); -+ ltq_rcu_gphy_boot(1, fw_addr); -+ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+int spi_cs_is_valid(unsigned int bus, unsigned int cs) -+{ -+ if (bus) -+ return 0; -+ -+ if (cs == 4) -+ return 1; -+ -+ return 0; -+} -+ -+void spi_cs_activate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 0); -+ break; -+ default: -+ break; -+ } -+} -+ -+void spi_cs_deactivate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 1); -+ break; -+ default: -+ break; -+ } -+} ---- a/boards.cfg -+++ b/boards.cfg -@@ -517,6 +517,9 @@ Active mips mips32 incai - Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk -+Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck -+Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck -+Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck ---- /dev/null -+++ b/include/configs/fb3370.h -@@ -0,0 +1,78 @@ -+/* -+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "FB3370" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "AVM FritzBox 3370" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_SPI_FLASH -+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */ -+ -+#define CONFIG_LTQ_SUPPORT_NAND_FLASH -+ -+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ -+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ -+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ -+ -+#define CONFIG_SPL_SPI_BUS 0 -+#define CONFIG_SPL_SPI_CS 4 -+#define CONFIG_SPL_SPI_MAX_HZ 25000000 -+#define CONFIG_SPL_SPI_MODE 0 -+ -+#define CONFIG_SYS_DRAM_PROBE -+ -+/* Environment */ -+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS -+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS -+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ -+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE -+ -+#if defined(CONFIG_SYS_BOOT_SFSPL) -+#define CONFIG_ENV_IS_IN_SPI_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+#if defined(CONFIG_SYS_BOOT_EVA) -+#define CONFIG_SYS_TEXT_BASE 0x80100000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#endif -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY VRX200 */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_SF \ -+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_SF -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch b/package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch deleted file mode 100644 index 96737fa483..0000000000 --- a/package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch +++ /dev/null @@ -1,247 +0,0 @@ -From 9e9dec563e4d061e7b34d2d59a89eb05c60f43a7 Mon Sep 17 00:00:00 2001 -From: Luka Perkov -Date: Sat, 2 Mar 2013 23:34:00 +0100 -Subject: MIPS: add board support for Gigaset SX76X - -Signed-off-by: Luka Perkov -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/board/gigaset/sx76x/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/gigaset/sx76x/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/gigaset/sx76x/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2011-2013 Luka Perkov -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x202 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0xF3E -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x300 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA04 -+#define MC_DC21_VALUE 0xF00 -+#define MC_DC22_VALUE 0xF0F -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x63 -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x100 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x514 -+#define MC_DC29_VALUE 0x2D89 -+#define MC_DC30_VALUE 0x8300 -+#define MC_DC31_VALUE 0x2002 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- /dev/null -+++ b/board/gigaset/sx76x/sx76x.c -@@ -0,0 +1,65 @@ -+/* -+ * Copyright (C) 2011 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static void gpio_init(void) -+{ -+ /* Activate reset line of ADM6996I switch */ -+ gpio_direction_output(19, 0); -+} -+ -+int board_early_init_f(void) -+{ -+ gpio_init(); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Lantiq ADM6996I switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device adm6996i_dev = { -+ .name = "adm6996i", -+ .cpu_port = 5, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ /* Deactivate reset line of ADM6996I switch */ -+ gpio_set_value(19, 1); -+ -+ /* ADM6996I needs some time to come out of reset */ -+ __udelay(50000); -+ -+ return switch_device_register(&adm6996i_dev); -+} ---- a/boards.cfg -+++ b/boards.cfg -@@ -510,6 +510,8 @@ Active mips mips32 danub - Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov - Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle - Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle -+Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov -+Active mips mips32 danube gigaset sx76x gigasx76x_ram sx76x:SYS_BOOT_RAM Luka Perkov - Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck - Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck ---- /dev/null -+++ b/include/configs/sx76x.h -@@ -0,0 +1,59 @@ -+/* -+ * Copyright (C) 2011-2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "GIGASX76X" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Gigaset sx76x" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_ADM6996I -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0040000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch b/package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch deleted file mode 100644 index a1c0bdede0..0000000000 --- a/package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch +++ /dev/null @@ -1,301 +0,0 @@ -From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001 -From: Luka Perkov -Date: Tue, 6 Aug 2013 22:51:00 +0200 -Subject: MIPS: add board support for ZyXEL P-2812HNU-Fx - -Signed-off-by: Luka Perkov - ---- /dev/null -+++ b/board/zyxel/p2812hnufx/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/zyxel/p2812hnufx/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/zyxel/p2812hnufx/ddr_settings.h -@@ -0,0 +1,70 @@ -+/* -+ * Copyright (C) 2013 Luka Perkov -+ * -+ * The values have been extracted from original ZyXEL U-Boot. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_CCR00_VALUE 0x101 -+#define MC_CCR01_VALUE 0x1000100 -+#define MC_CCR02_VALUE 0x1010000 -+#define MC_CCR03_VALUE 0x101 -+#define MC_CCR04_VALUE 0x1000000 -+#define MC_CCR05_VALUE 0x1000101 -+#define MC_CCR06_VALUE 0x1000100 -+#define MC_CCR07_VALUE 0x1010000 -+#define MC_CCR08_VALUE 0x1000101 -+#define MC_CCR09_VALUE 0x0 -+#define MC_CCR10_VALUE 0x2000100 -+#define MC_CCR11_VALUE 0x2000300 -+#define MC_CCR12_VALUE 0x30000 -+#define MC_CCR13_VALUE 0x202 -+#define MC_CCR14_VALUE 0x7080A0F -+#define MC_CCR15_VALUE 0x2040F -+#define MC_CCR16_VALUE 0x40000 -+#define MC_CCR17_VALUE 0x70102 -+#define MC_CCR18_VALUE 0x4020002 -+#define MC_CCR19_VALUE 0x30302 -+#define MC_CCR20_VALUE 0x8000700 -+#define MC_CCR21_VALUE 0x40F020A -+#define MC_CCR22_VALUE 0x0 -+#define MC_CCR23_VALUE 0xC020000 -+#define MC_CCR24_VALUE 0x4401B04 -+#define MC_CCR25_VALUE 0x0 -+#define MC_CCR26_VALUE 0x0 -+#define MC_CCR27_VALUE 0x6420000 -+#define MC_CCR28_VALUE 0x0 -+#define MC_CCR29_VALUE 0x0 -+#define MC_CCR30_VALUE 0x798 -+#define MC_CCR31_VALUE 0x0 -+#define MC_CCR32_VALUE 0x0 -+#define MC_CCR33_VALUE 0x650000 -+#define MC_CCR34_VALUE 0x200C8 -+#define MC_CCR35_VALUE 0x1D445D -+#define MC_CCR36_VALUE 0xC8 -+#define MC_CCR37_VALUE 0xC351 -+#define MC_CCR38_VALUE 0x0 -+#define MC_CCR39_VALUE 0x141F04 -+#define MC_CCR40_VALUE 0x142704 -+#define MC_CCR41_VALUE 0x141B42 -+#define MC_CCR42_VALUE 0x141B42 -+#define MC_CCR43_VALUE 0x566504 -+#define MC_CCR44_VALUE 0x566504 -+#define MC_CCR45_VALUE 0x565F17 -+#define MC_CCR46_VALUE 0x565F17 -+#define MC_CCR47_VALUE 0x0 -+#define MC_CCR48_VALUE 0x0 -+#define MC_CCR49_VALUE 0x0 -+#define MC_CCR50_VALUE 0x0 -+#define MC_CCR51_VALUE 0x0 -+#define MC_CCR52_VALUE 0x133 -+#define MC_CCR53_VALUE 0xF3014B27 -+#define MC_CCR54_VALUE 0xF3014B27 -+#define MC_CCR55_VALUE 0xF3014B27 -+#define MC_CCR56_VALUE 0xF3014B27 -+#define MC_CCR57_VALUE 0x7800301 -+#define MC_CCR58_VALUE 0x7800301 -+#define MC_CCR59_VALUE 0x7800301 -+#define MC_CCR60_VALUE 0x7800301 -+#define MC_CCR61_VALUE 0x4 ---- /dev/null -+++ b/board/zyxel/p2812hnufx/p2812hnufx.c -@@ -0,0 +1,97 @@ -+/* -+ * Copyright (C) 2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_SPL_BUILD) -+#define do_gpio_init 1 -+#define do_pll_init 1 -+#define do_dcdc_init 0 -+#elif defined(CONFIG_SYS_BOOT_RAM) -+#define do_gpio_init 1 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#else -+#define do_gpio_init 0 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#endif -+ -+static void gpio_init(void) -+{ -+ /* EBU.FL_CS1 as output for NAND CE */ -+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A23 as output for NAND CLE */ -+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* EBU.FL_A24 as output for NAND ALE */ -+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* GPIO 3.0 as input for NAND Ready Busy */ -+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); -+ /* GPIO 3.1 as output for NAND Read */ -+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+} -+ -+int board_early_init_f(void) -+{ -+ if (do_gpio_init) -+ gpio_init(); -+ -+ if (do_pll_init) -+ ltq_pll_init(); -+ -+ if (do_dcdc_init) -+ ltq_dcdc_init(0x7F); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ -+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ -+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ -+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, -+ /* GMAC3: unused */ -+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, -+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ -+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, -+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ -+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t * bis) -+{ -+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; -+ const ulong fw_addr = 0x80FF0000; -+ -+ ltq_gphy_phy11g_a1x_load(fw_addr); -+ -+ ltq_cgu_gphy_clk_src(clk); -+ -+ ltq_rcu_gphy_boot(0, fw_addr); -+ ltq_rcu_gphy_boot(1, fw_addr); -+ -+ return ltq_eth_initialize(ð_board_config); -+} ---- a/boards.cfg -+++ b/boards.cfg -@@ -527,6 +527,8 @@ Active mips mips32 vrx20 - Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck - Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck -+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_nandspl p2812hnufx:SYS_BOOT_NANDSPL Luka Perkov -+Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_ram p2812hnufx:SYS_BOOT_RAM Luka Perkov - Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - - Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - - Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes ---- /dev/null -+++ b/include/configs/p2812hnufx.h -@@ -0,0 +1,67 @@ -+/* -+ * Copyright (C) 2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "P-2812HNU-Fx" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "ZyXEL P-2812HNU-Fx" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a K9F1G08U0D NAND flash */ -+ -+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ -+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ -+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ -+ -+#define CONFIG_SYS_NAND_PAGE_COUNT 64 -+#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -+#define CONFIG_SYS_NAND_OOBSIZE 64 -+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 -+ -+#define CONFIG_SYS_DRAM_PROBE -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NANDSPL) -+#define CONFIG_ENV_IS_IN_NAND -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SECT_SIZE (128 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY VRX200 */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NAND \ -+ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NAND -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch b/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch deleted file mode 100644 index 676ef12a8a..0000000000 --- a/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch +++ /dev/null @@ -1,242 +0,0 @@ -From fbdbf2ddf2b34d675d53de679c179788b0604c1a Mon Sep 17 00:00:00 2001 -From: Oliver Muth -Date: Sat, 12 Oct 2013 16:49:53 +0200 -Subject: MIPS: add board support for Arcadyan ARV752DPW - -Signed-off-by: Oliver Muth -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/board/arcadyan/arv752dpw/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/arcadyan/arv752dpw/arv752dpw.c -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (C) 2012 Luka Perkov -+ * Copyright (C) 2013 Oliver Muth -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_early_init_f(void) -+{ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Realtek rtl8306 switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+static struct switch_device rtl8306_dev = { -+ .name = "rtl8306", -+ .cpu_port = 5, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ return switch_device_register(&rtl8306_dev); -+} ---- /dev/null -+++ b/board/arcadyan/arv752dpw/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/arcadyan/arv752dpw/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2011-2013 Luka Perkov -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x134 -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x301 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA03 -+#define MC_DC21_VALUE 0x1400 -+#define MC_DC22_VALUE 0x1414 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x5B -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x4E20 -+#define MC_DC30_VALUE 0x8235 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- a/boards.cfg -+++ b/boards.cfg -@@ -518,6 +518,9 @@ Active mips mips32 danub - Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov -+Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN - -+Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR - -+Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM - - Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle - Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle - Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov ---- /dev/null -+++ b/include/configs/arv752dpw.h -@@ -0,0 +1,67 @@ -+/* -+ * Copyright (C) 2012-2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ARV752DPW" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_RTL8206 -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Brnboot loadable image */ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_OVERWRITE 1 -+#endif -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0040000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch b/package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch deleted file mode 100644 index 2cf0e95e34..0000000000 --- a/package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch +++ /dev/null @@ -1,244 +0,0 @@ -From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001 -From: Oliver Muth -Date: Sat, 12 Oct 2013 16:49:53 +0200 -Subject: MIPS: add board support for Arcadyan ARV752DPW22 - -Signed-off-by: Oliver Muth -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/board/arcadyan/arv752dpw22/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/arcadyan/arv752dpw22/arv752dpw22.c -@@ -0,0 +1,52 @@ -+/* -+ * Copyright (C) 2012 Luka Perkov -+ * Copyright (C) 2013 Oliver Muth -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_early_init_f(void) -+{ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Atheros ar8216 switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device ar8216_dev = { -+ .name = "ar8216", -+ .cpu_port = 0, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ return switch_device_register(&ar8216_dev); -+} ---- /dev/null -+++ b/board/arcadyan/arv752dpw22/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/arcadyan/arv752dpw22/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2011-2013 Luka Perkov -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x134 -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x301 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA03 -+#define MC_DC21_VALUE 0x1400 -+#define MC_DC22_VALUE 0x1414 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x5B -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x4E20 -+#define MC_DC30_VALUE 0x8235 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- a/boards.cfg -+++ b/boards.cfg -@@ -521,6 +521,9 @@ Active mips mips32 danub - Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN - - Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR - - Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM - -+Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN - -+Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR - -+Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM - - Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle - Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle - Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov ---- /dev/null -+++ b/include/configs/arv752dpw22.h -@@ -0,0 +1,68 @@ -+/* -+ * Copyright (C) 2012-2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ARV752DPW22" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW22" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_AR8216 -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Burnboot loadable image */ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_OVERWRITE 1 -+#endif -+ -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0040000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch b/package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch deleted file mode 100644 index 76f89550cc..0000000000 --- a/package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch +++ /dev/null @@ -1,269 +0,0 @@ -From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001 -From: Matti Laakso -Date: Sat, 2 Mar 2013 23:34:00 +0100 -Subject: MIPS: add board support for Arcadyan ARV7510 - -Signed-off-by: Matti Laakso -Signed-off-by: Daniel Schwierzeck - ---- /dev/null -+++ b/board/arcadyan/arv7510pw/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/arcadyan/arv7510pw/arv7510pw.c -@@ -0,0 +1,72 @@ -+/* -+ * Copyright (C) 2013 Matti Laakso -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static void gpio_init(void) -+{ -+ /* Initialize SSIO GPIOs */ -+ gpio_set_altfunc(4, 1, 0, 1); -+ gpio_set_altfunc(5, 1, 0, 1); -+ gpio_set_altfunc(6, 1, 0, 1); -+ ltq_gpio_init(); -+ -+ /* Power led on */ -+ gpio_direction_output(76, 1); -+} -+ -+int board_early_init_f(void) -+{ -+ gpio_init(); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: ADM6996I */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device adm6996i_dev = { -+ .name = "adm6996i", -+ .cpu_port = 5, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ /* Deactivate HRST line to release reset of ADM6996I switch */ -+ ltq_reset_once(LTQ_RESET_HARD, 200000); -+ -+ /* ADM6996I needs some time to come out of reset */ -+ __udelay(50000); -+ -+ return switch_device_register(&adm6996i_dev); -+} ---- /dev/null -+++ b/board/arcadyan/arv7510pw/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/arcadyan/arv7510pw/ddr_settings.h -@@ -0,0 +1,53 @@ -+/* -+ * Copyright (C) 2013 Matti Laakso -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x120 -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x301 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA04 -+#define MC_DC21_VALUE 0x1700 -+#define MC_DC22_VALUE 0x1717 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x52 -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x4E20 -+#define MC_DC30_VALUE 0x8235 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- a/boards.cfg -+++ b/boards.cfg -@@ -515,6 +515,9 @@ Active mips mips32 au1x0 - Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov - Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov - Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov -+Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov -+Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov -+Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov ---- /dev/null -+++ b/include/configs/arv7510pw.h -@@ -0,0 +1,75 @@ -+/* -+ * Copyright (C) 2013 Matti Laakso -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ARV7510PW" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_ADM6996I -+ -+/* SSIO */ -+#define CONFIG_LTQ_SSIO_SHIFT_REGS -+#define CONFIG_LTQ_SSIO_EDGE_FALLING -+#define CONFIG_LTQ_SSIO_GPHY1_MODE 0 -+#define CONFIG_LTQ_SSIO_GPHY2_MODE 0 -+#define CONFIG_LTQ_SSIO_INIT_VALUE 0 -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SECT_SIZE (128 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Brnboot loadable image */ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_OVERWRITE 1 -+#endif -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Buffered write broken in ARV7510PW */ -+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0060000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0041-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch b/package/boot/uboot-lantiq/patches/0041-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch deleted file mode 100644 index f8669211ab..0000000000 --- a/package/boot/uboot-lantiq/patches/0041-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch +++ /dev/null @@ -1,238 +0,0 @@ ---- /dev/null -+++ b/board/arcadyan/arv7510pw22/arv7510pw22.c -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2014 Álvaro Fernández Rojas -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_early_init_f(void) -+{ -+ /* Switch on Power LED */ -+ gpio_direction_output(2, 0); -+ gpio_set_value(2, 0); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Atheros ar8216 switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device ar8216_dev = { -+ .name = "ar8216", -+ .cpu_port = 0, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ return switch_device_register(&ar8216_dev); -+} ---- /dev/null -+++ b/board/arcadyan/arv7510pw22/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/arcadyan/arv7510pw22/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2014 Álvaro Fernández Rojas -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x134 -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x301 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA03 -+#define MC_DC21_VALUE 0x1400 -+#define MC_DC22_VALUE 0x1414 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x5B -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x4E20 -+#define MC_DC30_VALUE 0x8235 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- /dev/null -+++ b/board/arcadyan/arv7510pw22/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- a/boards.cfg -+++ b/boards.cfg -@@ -518,6 +518,9 @@ Active mips mips32 danub - Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov - Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov - Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov -+Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_brn arv7510pw22:SYS_BOOT_BRN Álvaro Fernández Rojas -+Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_nor arv7510pw22:SYS_BOOT_NOR Álvaro Fernández Rojas -+Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_ram arv7510pw22:SYS_BOOT_RAM Álvaro Fernández Rojas - Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov - Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov ---- /dev/null -+++ b/include/configs/arv7510pw22.h -@@ -0,0 +1,67 @@ -+/* -+ * Copyright (C) 2014 Álvaro Fernández Rojas -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ARV7510PW22" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW22" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_AR8216 -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SECT_SIZE (128 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Burnboot loadable image */ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_OVERWRITE 1 -+#endif -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0060000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0041-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch b/package/boot/uboot-lantiq/patches/0041-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch deleted file mode 100644 index 1f89e54608..0000000000 --- a/package/boot/uboot-lantiq/patches/0041-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch +++ /dev/null @@ -1,18 +0,0 @@ -From 7e2f79bc40b572763a4a1ed69f63aa2eaa6df254 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck -Date: Sun, 20 Oct 2013 19:39:17 +0200 -Subject: Makefile: prepare u-boot-lantiq-v2013.10-openwrt4 - -Signed-off-by: Daniel Schwierzeck - ---- a/Makefile -+++ b/Makefile -@@ -8,7 +8,7 @@ - VERSION = 2013 - PATCHLEVEL = 10 - SUBLEVEL = --EXTRAVERSION = -+EXTRAVERSION = -openwrt4 - ifneq "$(SUBLEVEL)" "" - U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) - else diff --git a/package/boot/uboot-lantiq/patches/0041-lzma-fixup.patch b/package/boot/uboot-lantiq/patches/0041-lzma-fixup.patch deleted file mode 100644 index 5b16758fa4..0000000000 --- a/package/boot/uboot-lantiq/patches/0041-lzma-fixup.patch +++ /dev/null @@ -1,44 +0,0 @@ -From: Antonios Vamporakis -Date: Tue, 31 Dec 2013 01:05:42 +0100 -Subject: [PATCH] lzma: fix buffer bound check error - -Variable uncompressedSize references the space available, while outSizeFull is -the actual expected uncompressed size. Using the wrong value causes LzmaDecode -to return SZ_ERROR_INPUT_EOF. Problem was introduced in commit afca294. While -at it add additional debug message. - -Signed-off-by: Antonios Vamporakis -CC: Kees Cook -CC: Simon Glass -CC: Daniel Schwierzeck -CC: Luka Perkov ---- - lib/lzma/LzmaTools.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/lib/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c -index 0aec2f9..90d31cd 100644 ---- a/lib/lzma/LzmaTools.c -+++ b/lib/lzma/LzmaTools.c -@@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize, - return SZ_ERROR_OUTPUT_EOF; - - /* Decompress */ -- outProcessed = *uncompressedSize; -+ outProcessed = outSizeFull; - - WATCHDOG_RESET(); - -@@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize, - inStream + LZMA_DATA_OFFSET, &compressedSize, - inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc); - *uncompressedSize = outProcessed; -+ -+ debug("LZMA: Uncompresed ................ 0x%zx\n", outProcessed); -+ - if (res != SZ_OK) { - return res; - } --- -1.8.3.2 - diff --git a/package/boot/uboot-lantiq/patches/0042-arx100-cgu-fixes.patch b/package/boot/uboot-lantiq/patches/0042-arx100-cgu-fixes.patch deleted file mode 100644 index 8ca6a1e038..0000000000 --- a/package/boot/uboot-lantiq/patches/0042-arx100-cgu-fixes.patch +++ /dev/null @@ -1,148 +0,0 @@ -From patchwork Tue Jan 20 11:28:45 2015 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image -From: Ben Mulvihill -X-Patchwork-Id: 431024 -Message-Id: <1421753325.25187.58.camel@merveille.lan> -To: Daniel Schwierzeck -Cc: OpenWrt Development List -Date: Tue, 20 Jan 2015 12:28:45 +0100 - -On Tue, 2015-01-20 at 00:39 +0100, Ben Mulvihill wrote: -> On Mon, 2015-01-19 at 19:21 +0100, Ben Mulvihill wrote: -> > On Mon, 2015-01-19 at 16:47 +0100, Daniel Schwierzeck wrote: -> > > 2015-01-19 15:44 GMT+01:00 Ben Mulvihill : -> > > > On Mon, 2015-01-19 at 11:51 +0000, Conor O'Gorman wrote: -> > > >> On 19/01/15 10:46, Ben Mulvihill wrote: -> > > >> > Hello, -> > > >> > -> > > >> > I am trying to build uboot-lantiq for the BT Home Hub 3A (lantiq -> > > >> > ar9), and am wondering where to initialise the cgu, in the case -> > > >> > of a ramboot image for uart booting. Normally the cgu is initialised -> > > >> > in lowlevel_init, but that code is bypassed in ramboot images. The -> > > >> > result is that the board boots with the wrong cgu settings, which -> > > >> > sends the console haywire. So far I have tried two solutions: -> > > >> -> > > >> Another option is to try and not change anything. The console is already -> > > >> configured and running. The ram does need config. -> > > >> -> > > >> I was used to seeing the ramboot version running at half clock speed, at -> > > >> least on danube, previous to ar9. -> > > >> -> > > >> Conor -> > > > -> > > > Hi Conor, -> > > > -> > > > Thanks for the reply. But with the latest uboot-lantiq, not changing -> > > > anything means that I don't get a usable console. With an older -> > > > version I do at least get a uboot console, but no linux console when -> > > > I boot openwrt. Correcting the cgu settings solves both problems. -> > > > -> > > -> > > could you try this? -> > > -> > > diff --git a/arch/mips/cpu/mips32/arx100/cgu.c -> > > b/arch/mips/cpu/mips32/arx100/cgu.c -> > > index 6e71ee7..e0afbda 100644 -> > > --- a/arch/mips/cpu/mips32/arx100/cgu.c -> > > +++ b/arch/mips/cpu/mips32/arx100/cgu.c -> > > @@ -95,15 +95,5 @@ unsigned long ltq_get_cpu_clock(void) -> > > -> > > unsigned long ltq_get_bus_clock(void) -> > > { -> > > - u32 fpi_sel; -> > > - unsigned long clk; -> > > - -> > > - fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL); -> > > - -> > > - if (fpi_sel) -> > > - clk = ltq_get_io_region_clock() / 2; -> > > - else -> > > - clk = ltq_get_io_region_clock(); -> > > - -> > > - return clk; -> > > + return ltq_get_io_region_clock(); -> > > } -> > > -> > > the UART driver calculates the baudrate from the FPI bus clock, but -> > > FPI_SEL is not available on AR9. FPI bus clock is always the same as -> > > DDR clock, Obviously a copy&paste error from VR9 code ;) -> > > -> > -> > No, even with this patch, I still don't get a working console I'm -> > afraid. If I don't set anything explicitly, the board comes up with -> > CGU_SYS set to 0x05, ie CGU_SYS_SYSSEL_PLL0_333_MHZ | -> > CGU_SYS_CPUSEL_EQUAL_DDRCLK | CGU_SYS_DDRSEL_THIRD_SYSCLK. -> > Is this a valid combination without CGU_SYS_PPESEL_250_MHZ ? -> > I don't understand what CGU_SYS_PPESEL_250_MHZ does? -> > The "right setting", as set by the stock uboot, is 0x80. -> -> P.S. There also seems to be a discrepancy between the uboot and -> linux code. I take it from what you say above that fpi clock, ddr -> clock and io region clock are all the same. Now if the least -> significant bit of CGU_SYS is set, then according to the uboot -> code - function ltq_get_bus_clock() - their value is one -> third of the system clock. But according to the linux code -> - function ltq_ar9_fpi_hz() in arch/mips/lantiq/xway/clk.c - -> their value in this case is equal to the system clock. -> -> Or am I getting muddled? It's past my bedtime! -> -> - -Some of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1 -out. A patch along these lines should fix it: - ---- a/arch/mips/cpu/mips32/arx100/cgu.c 2015-01-20 11:57:22.000000000 +0100 -+++ b/arch/mips/cpu/mips32/arx100/cgu.c 2015-01-20 12:00:15.000000000 +0100 -@@ -10,12 +10,17 @@ - #include - #include - --#define CGU_SYS_DDR_SEL (1 << 0) --#define CGU_SYS_CPU_SEL (1 << 2) -+#define CGU_SYS_DDR_SHIFT 0 -+#define CGU_SYS_CPU_SHIFT 2 - #define CGU_SYS_SYS_SHIFT 3 -+#define CGU_SYS_FPI_SHIFT 6 -+#define CGU_SYS_PPE_SHIFT 7 -+ -+#define CGU_SYS_DDR_MASK (1 << CGU_SYS_DDR_SHIFT) -+#define CGU_SYS_CPU_MASK (1 << CGU_SYS_CPU_SHIFT) - #define CGU_SYS_SYS_MASK (0x3 << CGU_SYS_SYS_SHIFT) --#define CGU_SYS_FPI_SEL (1 << 6) --#define CGU_SYS_PPE_SEL (1 << 7) -+#define CGU_SYS_FPI_MASK (1 << CGU_SYS_FPI_SHIFT) -+#define CGU_SYS_PPE_MASK (1 << CGU_SYS_PPE_SHIFT) - - struct ltq_cgu_regs { - u32 rsvd0; -@@ -68,7 +73,7 @@ unsigned long ltq_get_io_region_clock(vo - u32 ddr_sel; - unsigned long clk; - -- ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL); -+ ddr_sel = ltq_cgu_sys_readl(CGU_SYS_DDR_MASK, CGU_SYS_DDR_SHIFT); - - if (ddr_sel) - clk = ltq_get_system_clock() / 3; -@@ -83,7 +88,7 @@ unsigned long ltq_get_cpu_clock(void) - u32 cpu_sel; - unsigned long clk; - -- cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL); -+ cpu_sel = ltq_cgu_sys_readl(CGU_SYS_CPU_MASK, CGU_SYS_CPU_SHIFT); - - if (cpu_sel) - clk = ltq_get_io_region_clock(); -@@ -98,7 +103,7 @@ unsigned long ltq_get_bus_clock(void) - u32 fpi_sel; - unsigned long clk; - -- fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL); -+ fpi_sel = ltq_cgu_sys_readl(CGU_SYS_FPI_MASK, CGU_SYS_FPI_SHIFT); - - if (fpi_sel) - clk = ltq_get_io_region_clock() / 2; diff --git a/package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch b/package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch deleted file mode 100644 index eb688a9caa..0000000000 --- a/package/boot/uboot-lantiq/patches/0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch +++ /dev/null @@ -1,346 +0,0 @@ ---- /dev/null -+++ b/board/arcadyan/vgv7510kw22/Makefile -@@ -0,0 +1,27 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### ---- /dev/null -+++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c -@@ -0,0 +1,136 @@ -+/* -+ * Copyright (C) 2015 Martin Blumenstingl -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_SPL_BUILD) -+#define do_gpio_init 1 -+#define do_pll_init 1 -+#define do_dcdc_init 0 -+#elif defined(CONFIG_SYS_BOOT_RAM) -+#define do_gpio_init 1 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#elif defined(CONFIG_SYS_BOOT_NOR) -+#define do_gpio_init 1 -+#define do_pll_init 1 -+#define do_dcdc_init 1 -+#else -+#define do_gpio_init 0 -+#define do_pll_init 0 -+#define do_dcdc_init 1 -+#endif -+ -+#define GPIO_POWER_GREEN 14 -+ -+static void gpio_init(void) -+{ -+ /* SPI CS 0.4 to serial flash */ -+ gpio_direction_output(10, 1); -+ -+ /* Turn on the green power LED */ -+ gpio_direction_output(GPIO_POWER_GREEN, 0); -+ gpio_set_value(GPIO_POWER_GREEN, 0); -+} -+ -+int board_early_init_f(void) -+{ -+ if (do_gpio_init) -+ gpio_init(); -+ -+ if (do_pll_init) -+ ltq_pll_init(); -+ -+ if (do_dcdc_init) -+ ltq_dcdc_init(0x7F); -+ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* unused */ -+ { 0, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, -+ /* unused */ -+ { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, -+ /* Internal GPHY0 with 10/100 firmware for LAN port 2 */ -+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, -+ /* Internal GPHY0 with 10/100 firmware for LAN port 1 */ -+ { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, -+ /* Internal GPHY1 with 10/100 firmware for LAN port 4 */ -+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, -+ /* Internal GPHY1 with 10/100 firmware for LAN port 3 */ -+ { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t * bis) -+{ -+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; -+ const ulong fw_addr = 0x80FF0000; -+ -+ if (ltq_chip_version_get() == 1) -+ ltq_gphy_phy22f_a1x_load(fw_addr); -+ else -+ ltq_gphy_phy22f_a2x_load(fw_addr); -+ -+ ltq_cgu_gphy_clk_src(clk); -+ -+ ltq_rcu_gphy_boot(0, fw_addr); -+ ltq_rcu_gphy_boot(1, fw_addr); -+ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+int spi_cs_is_valid(unsigned int bus, unsigned int cs) -+{ -+ if (bus) -+ return 0; -+ -+ if (cs == 4) -+ return 1; -+ -+ return 0; -+} -+ -+void spi_cs_activate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 0); -+ break; -+ default: -+ break; -+ } -+} -+ -+void spi_cs_deactivate(struct spi_slave *slave) -+{ -+ switch (slave->cs) { -+ case 4: -+ gpio_set_value(10, 1); -+ break; -+ default: -+ break; -+ } -+} ---- /dev/null -+++ b/board/arcadyan/vgv7510kw22/config.mk -@@ -0,0 +1,7 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ---- /dev/null -+++ b/board/arcadyan/vgv7510kw22/ddr_settings.h -@@ -0,0 +1,71 @@ -+/* -+ * Copyright (C) 2015 Martin Blumenstingl -+ * Based on code by: -+ * Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ * and Lantiq Deutschland GmbH -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_CCR00_VALUE 0x101 -+#define MC_CCR01_VALUE 0x1000100 -+#define MC_CCR02_VALUE 0x1010000 -+#define MC_CCR03_VALUE 0x100 -+#define MC_CCR04_VALUE 0x1000000 -+#define MC_CCR05_VALUE 0x1000101 -+#define MC_CCR06_VALUE 0x1000100 -+#define MC_CCR07_VALUE 0x1010000 -+#define MC_CCR08_VALUE 0x1000101 -+#define MC_CCR09_VALUE 0x0 -+#define MC_CCR10_VALUE 0x2000100 -+#define MC_CCR11_VALUE 0x2000401 -+#define MC_CCR12_VALUE 0x30000 -+#define MC_CCR13_VALUE 0x202 -+#define MC_CCR14_VALUE 0x7080A0F -+#define MC_CCR15_VALUE 0x2040F -+#define MC_CCR16_VALUE 0x40000 -+#define MC_CCR17_VALUE 0x70102 -+#define MC_CCR18_VALUE 0x4020002 -+#define MC_CCR19_VALUE 0x30302 -+#define MC_CCR20_VALUE 0x8000700 -+#define MC_CCR21_VALUE 0x40F020A -+#define MC_CCR22_VALUE 0x0 -+#define MC_CCR23_VALUE 0xC020000 -+#define MC_CCR24_VALUE 0x4401B04 -+#define MC_CCR25_VALUE 0x0 -+#define MC_CCR26_VALUE 0x0 -+#define MC_CCR27_VALUE 0x6420000 -+#define MC_CCR28_VALUE 0x0 -+#define MC_CCR29_VALUE 0x0 -+#define MC_CCR30_VALUE 0x798 -+#define MC_CCR31_VALUE 0x0 -+#define MC_CCR32_VALUE 0x0 -+#define MC_CCR33_VALUE 0x650000 -+#define MC_CCR34_VALUE 0x200C8 -+#define MC_CCR35_VALUE 0x1D445D -+#define MC_CCR36_VALUE 0xC8 -+#define MC_CCR37_VALUE 0xC351 -+#define MC_CCR38_VALUE 0x0 -+#define MC_CCR39_VALUE 0x141F04 -+#define MC_CCR40_VALUE 0x142704 -+#define MC_CCR41_VALUE 0x141B42 -+#define MC_CCR42_VALUE 0x141B42 -+#define MC_CCR43_VALUE 0x566504 -+#define MC_CCR44_VALUE 0x566504 -+#define MC_CCR45_VALUE 0x565F17 -+#define MC_CCR46_VALUE 0x565F17 -+#define MC_CCR47_VALUE 0x0 -+#define MC_CCR48_VALUE 0x0 -+#define MC_CCR49_VALUE 0x0 -+#define MC_CCR50_VALUE 0x0 -+#define MC_CCR51_VALUE 0x0 -+#define MC_CCR52_VALUE 0x133 -+#define MC_CCR53_VALUE 0xF3014B27 -+#define MC_CCR54_VALUE 0xF3014B27 -+#define MC_CCR55_VALUE 0xF3014B27 -+#define MC_CCR56_VALUE 0xF3014B27 -+#define MC_CCR57_VALUE 0x7800301 -+#define MC_CCR58_VALUE 0x7800301 -+#define MC_CCR59_VALUE 0x7800301 -+#define MC_CCR60_VALUE 0x7800301 -+#define MC_CCR61_VALUE 0x4 ---- a/boards.cfg -+++ b/boards.cfg -@@ -531,6 +531,9 @@ Active mips mips32 incai - Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk - Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk -+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl -+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl -+Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl - Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck - Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck - Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck ---- /dev/null -+++ b/include/configs/vgv7510kw22.h -@@ -0,0 +1,78 @@ -+/* -+ * Copyright (C) 2015 Martin Blumenstingl -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "VGV7510KW22" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Arcadyan VGV7510KW22" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+#define CONFIG_LTQ_SUPPORT_SPI_FLASH -+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29GL128EL parallel flash */ -+ -+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ -+#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ -+#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ -+ -+#define CONFIG_SPL_SPI_BUS 0 -+#define CONFIG_SPL_SPI_CS 4 -+#define CONFIG_SPL_SPI_MAX_HZ 25000000 -+#define CONFIG_SPL_SPI_MODE 0 -+ -+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ -+ -+#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */ -+ -+/* Environment */ -+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS -+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS -+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ -+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE -+ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_IS_NOWHERE -+#elif defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (384 * 1024) -+#define CONFIG_ENV_SECT_SIZE (128 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (128 * 1024) -+ -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyLTQ1" -+ -+/* Pull in default board configs for Lantiq XWAY VRX200 */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ "kernel_addr=0xB0080000\0" -+ -+#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0044-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch b/package/boot/uboot-lantiq/patches/0044-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch deleted file mode 100644 index 5cc71b615f..0000000000 --- a/package/boot/uboot-lantiq/patches/0044-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch +++ /dev/null @@ -1,240 +0,0 @@ ---- /dev/null -+++ b/board/arcadyan/arv8539pw22/Makefile -@@ -0,0 +1,28 @@ -+# -+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).o -+ -+COBJS = $(BOARD).o -+ -+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+SOBJS := $(addprefix $(obj),$(SOBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) $(SOBJS) -+ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -+ -+######################################################################### -+ ---- /dev/null -+++ b/board/arcadyan/arv8539pw22/arv8539pw22.c -@@ -0,0 +1,53 @@ -+/* -+ * Copyright (C) 2012 Luka Perkov -+ * Copyright (C) 2013 Oliver Muth -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_early_init_f(void) -+{ -+ return 0; -+} -+ -+int checkboard(void) -+{ -+ puts("Board: " CONFIG_BOARD_NAME "\n"); -+ ltq_chip_print_info(); -+ -+ return 0; -+} -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* MAC0: Atheros ar8216 switch */ -+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII }, -+}; -+ -+static const struct ltq_eth_board_config eth_board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+int board_eth_init(bd_t *bis) -+{ -+ return ltq_eth_initialize(ð_board_config); -+} -+ -+static struct switch_device ar8216_dev = { -+ .name = "ar8216", -+ .cpu_port = 0, -+ .port_mask = 0xF, -+}; -+ -+int board_switch_init(void) -+{ -+ return switch_device_register(&ar8216_dev); -+} -+ ---- /dev/null -+++ b/board/arcadyan/arv8539pw22/config.mk -@@ -0,0 +1,8 @@ -+# -+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) -+ ---- /dev/null -+++ b/board/arcadyan/arv8539pw22/ddr_settings.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright (C) 2011-2013 Luka Perkov -+ * -+ * This file has been generated with lantiq_ram_extract_magic.awk script. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#define MC_DC00_VALUE 0x1B1B -+#define MC_DC01_VALUE 0x0 -+#define MC_DC02_VALUE 0x0 -+#define MC_DC03_VALUE 0x0 -+#define MC_DC04_VALUE 0x0 -+#define MC_DC05_VALUE 0x200 -+#define MC_DC06_VALUE 0x605 -+#define MC_DC07_VALUE 0x303 -+#define MC_DC08_VALUE 0x102 -+#define MC_DC09_VALUE 0x70A -+#define MC_DC10_VALUE 0x203 -+#define MC_DC11_VALUE 0xC02 -+#define MC_DC12_VALUE 0x1C8 -+#define MC_DC13_VALUE 0x1 -+#define MC_DC14_VALUE 0x0 -+#define MC_DC15_VALUE 0x134 -+#define MC_DC16_VALUE 0xC800 -+#define MC_DC17_VALUE 0xD -+#define MC_DC18_VALUE 0x301 -+#define MC_DC19_VALUE 0x200 -+#define MC_DC20_VALUE 0xA03 -+#define MC_DC21_VALUE 0x1400 -+#define MC_DC22_VALUE 0x1414 -+#define MC_DC23_VALUE 0x0 -+#define MC_DC24_VALUE 0x5B -+#define MC_DC25_VALUE 0x0 -+#define MC_DC26_VALUE 0x0 -+#define MC_DC27_VALUE 0x0 -+#define MC_DC28_VALUE 0x510 -+#define MC_DC29_VALUE 0x4E20 -+#define MC_DC30_VALUE 0x8235 -+#define MC_DC31_VALUE 0x0 -+#define MC_DC32_VALUE 0x0 -+#define MC_DC33_VALUE 0x0 -+#define MC_DC34_VALUE 0x0 -+#define MC_DC35_VALUE 0x0 -+#define MC_DC36_VALUE 0x0 -+#define MC_DC37_VALUE 0x0 -+#define MC_DC38_VALUE 0x0 -+#define MC_DC39_VALUE 0x0 -+#define MC_DC40_VALUE 0x0 -+#define MC_DC41_VALUE 0x0 -+#define MC_DC42_VALUE 0x0 -+#define MC_DC43_VALUE 0x0 -+#define MC_DC44_VALUE 0x0 -+#define MC_DC45_VALUE 0x500 -+#define MC_DC46_VALUE 0x0 ---- a/boards.cfg -+++ b/boards.cfg -@@ -553,6 +553,9 @@ Active mips mips32 danube arcadyan arv752dpw - Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN - - Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR - - Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM - -+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_brn arv8539pw22:SYS_BOOT_BRN - -+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_nor arv8539pw22:SYS_BOOT_NOR - -+Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_ram arv8539pw22:SYS_BOOT_RAM - - Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle - Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle - Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov ---- /dev/null -+++ b/include/configs/arv8539pw22.h -@@ -0,0 +1,68 @@ -+/* -+ * Copyright (C) 2012-2013 Luka Perkov -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __CONFIG_H -+#define __CONFIG_H -+ -+#define CONFIG_MACH_TYPE "ARV8539PW22" -+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE -+#define CONFIG_BOARD_NAME "Speedport W 504V Typ A" -+ -+/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ -+ -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ -+ -+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ -+ -+/* Switch devices */ -+#define CONFIG_SWITCH_MULTI -+#define CONFIG_SWITCH_AR8216 -+ -+/* Environment */ -+#if defined(CONFIG_SYS_BOOT_NOR) -+#define CONFIG_ENV_IS_IN_FLASH -+#define CONFIG_ENV_OVERWRITE -+#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SECT_SIZE (64 * 1024) -+#else -+#define CONFIG_ENV_IS_NOWHERE -+#endif -+ -+#define CONFIG_ENV_SIZE (8 * 1024) -+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -+ -+/* Burnboot loadable image */ -+#if defined(CONFIG_SYS_BOOT_BRN) -+#define CONFIG_SYS_TEXT_BASE 0x80002000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#define CONFIG_SYS_DISABLE_CACHE -+#define CONFIG_ENV_OVERWRITE 1 -+#endif -+ -+ -+/* Console */ -+#define CONFIG_LTQ_ADVANCED_CONSOLE -+#define CONFIG_BAUDRATE 115200 -+#define CONFIG_CONSOLE_ASC 1 -+#define CONFIG_CONSOLE_DEV "ttyS1" -+ -+/* Pull in default board configs for Lantiq XWAY Danube */ -+#include -+#include -+ -+/* Pull in default OpenWrt configs for Lantiq SoC */ -+#include "openwrt-lantiq-common.h" -+ -+#define CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ -+ "kernel_addr=0xB0040000\0" -+ -+#endif /* __CONFIG_H */ - diff --git a/package/boot/uboot-lantiq/patches/0045-no_extern_inline.patch b/package/boot/uboot-lantiq/patches/0045-no_extern_inline.patch deleted file mode 100644 index 45e8b7d21d..0000000000 --- a/package/boot/uboot-lantiq/patches/0045-no_extern_inline.patch +++ /dev/null @@ -1,101 +0,0 @@ -From b11c5d1dc29e81326d1215011d19377737082aeb Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck -Date: Wed, 1 Jul 2015 16:36:43 +0200 -Subject: [PATCH] MIPS: change 'extern inline' to 'static inline' - -The kernel changed it a long time ago. Also this is now broken -on gcc-5.x. - -Reported-by: Andy Kennedy -Signed-off-by: Daniel Schwierzeck ---- - arch/mips/include/asm/io.h | 12 ++++++------ - arch/mips/include/asm/system.h | 6 +++--- - 2 files changed, 9 insertions(+), 9 deletions(-) - -diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h -index 3fa37f5..a7ab087 100644 ---- a/arch/mips/include/asm/io.h -+++ b/arch/mips/include/asm/io.h -@@ -117,7 +117,7 @@ static inline void set_io_port_base(unsigned long base) - * Change virtual addresses to physical addresses and vv. - * These are trivial on the 1:1 Linux/MIPS mapping - */ --extern inline phys_addr_t virt_to_phys(volatile void * address) -+static inline phys_addr_t virt_to_phys(volatile void * address) - { - #ifndef CONFIG_64BIT - return CPHYSADDR(address); -@@ -126,7 +126,7 @@ extern inline phys_addr_t virt_to_phys(volatile void * address) - #endif - } - --extern inline void * phys_to_virt(unsigned long address) -+static inline void * phys_to_virt(unsigned long address) - { - #ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -@@ -138,7 +138,7 @@ extern inline void * phys_to_virt(unsigned long address) - /* - * IO bus memory addresses are also 1:1 with the physical address - */ --extern inline unsigned long virt_to_bus(volatile void * address) -+static inline unsigned long virt_to_bus(volatile void * address) - { - #ifndef CONFIG_64BIT - return CPHYSADDR(address); -@@ -147,7 +147,7 @@ extern inline unsigned long virt_to_bus(volatile void * address) - #endif - } - --extern inline void * bus_to_virt(unsigned long address) -+static inline void * bus_to_virt(unsigned long address) - { - #ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -@@ -165,12 +165,12 @@ extern unsigned long isa_slot_offset; - extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); - - #if 0 --extern inline void *ioremap(unsigned long offset, unsigned long size) -+static inline void *ioremap(unsigned long offset, unsigned long size) - { - return __ioremap(offset, size, _CACHE_UNCACHED); - } - --extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) -+static inline void *ioremap_nocache(unsigned long offset, unsigned long size) - { - return __ioremap(offset, size, _CACHE_UNCACHED); - } -diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h -index 7a28952..d56f73b 100644 ---- a/arch/mips/include/asm/system.h -+++ b/arch/mips/include/asm/system.h -@@ -22,7 +22,7 @@ - #include - #endif - --extern __inline__ void -+static __inline__ void - __sti(void) - { - __asm__ __volatile__( -@@ -46,7 +46,7 @@ __sti(void) - * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs - * no nops at all. - */ --extern __inline__ void -+static __inline__ void - __cli(void) - { - __asm__ __volatile__( -@@ -207,7 +207,7 @@ do { \ - * For 32 and 64 bit operands we can take advantage of ll and sc. - * FIXME: This doesn't work for R3000 machines. - */ --extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) -+static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) - { - #ifdef CONFIG_CPU_HAS_LLSC - unsigned long dummy; diff --git a/package/boot/uboot-lantiq/patches/0046-no_weak_alias.patch b/package/boot/uboot-lantiq/patches/0046-no_weak_alias.patch deleted file mode 100644 index 4701ab1d24..0000000000 --- a/package/boot/uboot-lantiq/patches/0046-no_weak_alias.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 3422299dc28fa8257677d03cc1253e3c9bf17e9f Mon Sep 17 00:00:00 2001 -From: Jeroen Hofstee -Date: Thu, 26 Jun 2014 20:18:31 +0200 -Subject: [PATCH] common: main.c: make show_boot_progress __weak - -This not only looks a bit better it also prevents a -warning with W=1 (no previous prototype). - -Signed-off-by: Jeroen Hofstee -Acked-by: Simon Glass ---- - common/main.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/common/main.c b/common/main.c -index 32618f1..2979fbe 100644 ---- a/common/main.c -+++ b/common/main.c -@@ -17,8 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; - /* - * Board-specific Platform code can reimplement show_boot_progress () if needed - */ --void inline __show_boot_progress (int val) {} --void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); -+__weak void show_boot_progress(int val) {} - - static void modem_init(void) - { diff --git a/package/boot/uboot-lantiq/patches/0047-add-gcc5-support.patch b/package/boot/uboot-lantiq/patches/0047-add-gcc5-support.patch deleted file mode 100644 index 4d55f00a4e..0000000000 --- a/package/boot/uboot-lantiq/patches/0047-add-gcc5-support.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 478b02f1a7043b673565075ea5016376f3293b23 Mon Sep 17 00:00:00 2001 -From: Hans de Goede -Date: Sat, 7 Feb 2015 22:52:40 +0100 -Subject: [PATCH] Add linux/compiler-gcc5.h to fix builds with gcc5 - -Add linux/compiler-gcc5/h from the kernel sources at: - -commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b -Author: Steven Noonan -Date: Sat Oct 25 15:09:42 2014 -0700 - - compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles - -Signed-off-by: Hans de Goede ---- - include/linux/compiler-gcc5.h | 65 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 65 insertions(+) - create mode 100644 include/linux/compiler-gcc5.h - -diff --git a/include/linux/compiler-gcc5.h b/include/linux/compiler-gcc5.h -new file mode 100644 -index 0000000..c8c5659 ---- /dev/null -+++ b/include/linux/compiler-gcc5.h -@@ -0,0 +1,65 @@ -+#ifndef __LINUX_COMPILER_H -+#error "Please don't include directly, include instead." -+#endif -+ -+#define __used __attribute__((__used__)) -+#define __must_check __attribute__((warn_unused_result)) -+#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) -+ -+/* Mark functions as cold. gcc will assume any path leading to a call -+ to them will be unlikely. This means a lot of manual unlikely()s -+ are unnecessary now for any paths leading to the usual suspects -+ like BUG(), printk(), panic() etc. [but let's keep them for now for -+ older compilers] -+ -+ Early snapshots of gcc 4.3 don't support this and we can't detect this -+ in the preprocessor, but we can live with this because they're unreleased. -+ Maketime probing would be overkill here. -+ -+ gcc also has a __attribute__((__hot__)) to move hot functions into -+ a special section, but I don't see any sense in this right now in -+ the kernel context */ -+#define __cold __attribute__((__cold__)) -+ -+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) -+ -+#ifndef __CHECKER__ -+# define __compiletime_warning(message) __attribute__((warning(message))) -+# define __compiletime_error(message) __attribute__((error(message))) -+#endif /* __CHECKER__ */ -+ -+/* -+ * Mark a position in code as unreachable. This can be used to -+ * suppress control flow warnings after asm blocks that transfer -+ * control elsewhere. -+ * -+ * Early snapshots of gcc 4.5 don't support this and we can't detect -+ * this in the preprocessor, but we can live with this because they're -+ * unreleased. Really, we need to have autoconf for the kernel. -+ */ -+#define unreachable() __builtin_unreachable() -+ -+/* Mark a function definition as prohibited from being cloned. */ -+#define __noclone __attribute__((__noclone__)) -+ -+/* -+ * Tell the optimizer that something else uses this function or variable. -+ */ -+#define __visible __attribute__((externally_visible)) -+ -+/* -+ * GCC 'asm goto' miscompiles certain code sequences: -+ * -+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 -+ * -+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. -+ * -+ * (asm goto is automatically volatile - the naming reflects this.) -+ */ -+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) -+ -+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP -+#define __HAVE_BUILTIN_BSWAP32__ -+#define __HAVE_BUILTIN_BSWAP64__ -+#define __HAVE_BUILTIN_BSWAP16__ -+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ --- -1.7.10.4 - diff --git a/package/boot/uboot-lantiq/patches/0100-MIPS-add-board-support-for-Easy-50712.patch b/package/boot/uboot-lantiq/patches/0100-MIPS-add-board-support-for-Easy-50712.patch new file mode 100644 index 0000000000..9d6dc2d550 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0100-MIPS-add-board-support-for-Easy-50712.patch @@ -0,0 +1,306 @@ +--- /dev/null ++++ b/board/lantiq/easy50712/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/lantiq/easy50712/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/lantiq/easy50712/ddr_settings.h +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70a ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xc02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x13c ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xd ++#define MC_DC18_VALUE 0x300 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA04 ++#define MC_DC21_VALUE 0xd00 ++#define MC_DC22_VALUE 0xd0d ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x62 ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x2d89 ++#define MC_DC30_VALUE 0x8300 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- /dev/null ++++ b/board/lantiq/easy50712/easy50712.c +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (C) 2010 Thomas Langer ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void gpio_init(void) ++{ ++ /* SPI/CS output (low-active) for serial flash */ ++ gpio_direction_output(22, 1); ++ ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ ++ /* enable CLK_OUT2 for external switch */ ++ gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++} ++ ++int board_early_init_f(void) ++{ ++ gpio_init(); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Lantiq ADM6996I switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device adm6996i_dev = { ++ .name = "adm6996i", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ /* Deactivate HRST line to release reset of ADM6996I switch */ ++ ltq_reset_once(LTQ_RESET_HARD, 200000); ++ ++ /* ADM6996I needs some time to come out of reset */ ++ __udelay(50000); ++ ++ return switch_device_register(&adm6996i_dev); ++} ++ ++int spi_cs_is_valid(unsigned int bus, unsigned int cs) ++{ ++ if (bus) ++ return 0; ++ ++ switch (cs) { ++ case 2: ++ return 1; ++ default: ++ return 0; ++ } ++} ++ ++void spi_cs_activate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 2: ++ gpio_set_value(22, 0); ++ break; ++ default: ++ break; ++ } ++} ++ ++void spi_cs_deactivate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 2: ++ gpio_set_value(22, 1); ++ break; ++ default: ++ break; ++ } ++} +--- a/boards.cfg ++++ b/boards.cfg +@@ -502,6 +502,9 @@ Active mips mips32 au1x0 + Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange + Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange + Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - ++Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck ++Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck ++Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck + Active mips mips32 incaip - incaip incaip - Wolfgang Denk + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk +--- /dev/null ++++ b/include/configs/easy50712.h +@@ -0,0 +1,79 @@ ++/* ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "EASY50712" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Lantiq EASY50712 Danube Reference Board" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPI_FLASH ++#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */ ++ ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ ++ ++#define CONFIG_LTQ_SPL_COMP_LZO ++#define CONFIG_LTQ_SPL_CONSOLE ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_ADM6996I ++ ++/* Environment */ ++#define CONFIG_ENV_SPI_BUS 0 ++#define CONFIG_ENV_SPI_CS 2 ++#define CONFIG_ENV_SPI_MAX_HZ 20000000 ++#define CONFIG_ENV_SPI_MODE 0 ++ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#elif defined(CONFIG_SYS_BOOT_NORSPL) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (128 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++ ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0101-MIPS-add-board-support-for-Easy-80920.patch b/package/boot/uboot-lantiq/patches/0101-MIPS-add-board-support-for-Easy-80920.patch new file mode 100644 index 0000000000..fcc916333d --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0101-MIPS-add-board-support-for-Easy-80920.patch @@ -0,0 +1,379 @@ +--- /dev/null ++++ b/board/lantiq/easy80920/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/lantiq/easy80920/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/lantiq/easy80920/ddr_settings.h +@@ -0,0 +1,69 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000100 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x101 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x0 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000300 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401B04 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x0 ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1D445D ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x141F04 ++#define MC_CCR40_VALUE 0x142704 ++#define MC_CCR41_VALUE 0x141b42 ++#define MC_CCR42_VALUE 0x141b42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x0 ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7800301 ++#define MC_CCR58_VALUE 0x7800301 ++#define MC_CCR59_VALUE 0x7800301 ++#define MC_CCR60_VALUE 0x7800301 ++#define MC_CCR61_VALUE 0x4 +--- /dev/null ++++ b/board/lantiq/easy80920/easy80920.c +@@ -0,0 +1,138 @@ ++/* ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_SPL_BUILD) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 0 ++#elif defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#elif defined(CONFIG_SYS_BOOT_NOR) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++static void gpio_init(void) ++{ ++ /* SPI CS 0.4 to serial flash */ ++ gpio_direction_output(10, 1); ++ ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* GPIO 3.0 as input for NAND Ready Busy */ ++ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); ++ /* GPIO 3.1 as output for NAND Read */ ++ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ ++ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ ++ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ ++ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC3: unused */ ++ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ ++ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_addr = 0x80FF0000; ++ ++ ltq_gphy_phy11g_a1x_load(fw_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_addr); ++ ltq_rcu_gphy_boot(1, fw_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++int spi_cs_is_valid(unsigned int bus, unsigned int cs) ++{ ++ if (bus) ++ return 0; ++ ++ if (cs == 4) ++ return 1; ++ ++ return 0; ++} ++ ++void spi_cs_activate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 0); ++ break; ++ default: ++ break; ++ } ++} ++ ++void spi_cs_deactivate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 1); ++ break; ++ default: ++ break; ++ } ++} +--- a/boards.cfg ++++ b/boards.cfg +@@ -509,6 +509,11 @@ Active mips mips32 incai + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk ++Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck ++Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck ++Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck ++Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck ++Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck + Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - + Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - + Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes +--- /dev/null ++++ b/include/configs/easy80920.h +@@ -0,0 +1,109 @@ ++/* ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "EASY80920" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Lantiq EASY80920 VRX200 Family Board" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPI_FLASH ++#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */ ++ ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH ++ ++#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ ++#define CONFIG_SPL_SPI_BUS 0 ++#define CONFIG_SPL_SPI_CS 4 ++#define CONFIG_SPL_SPI_MAX_HZ 25000000 ++#define CONFIG_SPL_SPI_MODE 0 ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ ++#define CONFIG_SYS_NAND_PAGE_COUNT 128 ++#define CONFIG_SYS_NAND_PAGE_SIZE 2048 ++#define CONFIG_SYS_NAND_OOBSIZE 64 ++#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) ++#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS ++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 ++ ++#define CONFIG_LTQ_SPL_COMP_LZO ++#define CONFIG_LTQ_SPL_CONSOLE ++ ++#define CONFIG_SYS_DRAM_PROBE ++ ++/* Environment */ ++#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS ++#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS ++#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ ++#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE ++ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (384 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#elif defined(CONFIG_SYS_BOOT_NORSPL) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#elif defined(CONFIG_SYS_BOOT_SFSPL) ++#define CONFIG_ENV_IS_IN_SPI_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#elif defined(CONFIG_SYS_BOOT_NANDSPL) ++#define CONFIG_ENV_IS_IN_NAND ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (256 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++ ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_SF \ ++ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NAND \ ++ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ CONFIG_ENV_UPDATE_UBOOT_SF \ ++ CONFIG_ENV_UPDATE_UBOOT_NAND ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0102-MIPS-add-board-support-for-Arcadyan-ARV4519PW.patch b/package/boot/uboot-lantiq/patches/0102-MIPS-add-board-support-for-Arcadyan-ARV4519PW.patch new file mode 100644 index 0000000000..51738e40b8 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0102-MIPS-add-board-support-for-Arcadyan-ARV4519PW.patch @@ -0,0 +1,242 @@ +From 9f915cf9550a6234adecaf3031c2b279835e14af Mon Sep 17 00:00:00 2001 +From: Luka Perkov +Date: Sat, 2 Mar 2013 23:34:00 +0100 +Subject: MIPS: add board support for Arcadyan ARV4519 + +Signed-off-by: Luka Perkov +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/board/arcadyan/arv4519pw/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/arcadyan/arv4519pw/arv4519pw.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (C) 2012 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Atheros ar8216 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device ar8216_dev = { ++ .name = "ar8216", ++ .cpu_port = 0, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&ar8216_dev); ++} +--- /dev/null ++++ b/board/arcadyan/arv4519pw/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/arv4519pw/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x131 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA04 ++#define MC_DC21_VALUE 0x1700 ++#define MC_DC22_VALUE 0x1717 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5A ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- a/boards.cfg ++++ b/boards.cfg +@@ -502,6 +502,9 @@ Active mips mips32 au1x0 + Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange + Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange + Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - ++Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov ++Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov ++Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck +--- /dev/null ++++ b/include/configs/arv4519pw.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV4519PW" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV4519PW" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_AR8216 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0103-MIPS-add-board-support-for-Arcadyan-ARV7518PW.patch b/package/boot/uboot-lantiq/patches/0103-MIPS-add-board-support-for-Arcadyan-ARV7518PW.patch new file mode 100644 index 0000000000..21e6a2c5e9 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0103-MIPS-add-board-support-for-Arcadyan-ARV7518PW.patch @@ -0,0 +1,242 @@ +From 54a31b334162e8dc2ea891057ddeab42978db8b3 Mon Sep 17 00:00:00 2001 +From: Luka Perkov +Date: Sat, 2 Mar 2013 23:34:00 +0100 +Subject: MIPS: add board support for Arcadyan ARV7518 + +Signed-off-by: Luka Perkov +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/board/arcadyan/arv7518pw/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/arcadyan/arv7518pw/arv7518pw.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (C) 2012 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Atheros ar8216 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device ar8216_dev = { ++ .name = "ar8216", ++ .cpu_port = 0, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&ar8216_dev); ++} +--- /dev/null ++++ b/board/arcadyan/arv7518pw/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/arv7518pw/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x134 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1400 ++#define MC_DC22_VALUE 0x1414 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5B ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- a/boards.cfg ++++ b/boards.cfg +@@ -505,6 +505,9 @@ Active mips mips32 au1x0 + Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov + Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov + Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov ++Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov ++Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov ++Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck +--- /dev/null ++++ b/include/configs/arv7518pw.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV7518PW" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV7518PW" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_AR8216 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0104-MIPS-add-board-support-for-AudioCodes-MP-252.patch b/package/boot/uboot-lantiq/patches/0104-MIPS-add-board-support-for-AudioCodes-MP-252.patch new file mode 100644 index 0000000000..00820f8e3d --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0104-MIPS-add-board-support-for-AudioCodes-MP-252.patch @@ -0,0 +1,248 @@ +From 4bacfc80eae768be45f9ddf7588ec55281354648 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 8 Mar 2013 13:29:04 +0200 +Subject: MIPS: add board support for AudioCodes MP-252 + +Signed-off-by: Daniel Golle + +--- /dev/null ++++ b/board/audiocodes/acmp252/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/audiocodes/acmp252/acmp252.c +@@ -0,0 +1,66 @@ ++/* ++ * Copyright (C) 2013 Daniel Golle ++ * Copyright (C) 2011 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void gpio_init(void) ++{ ++ /* Activate reset line of ADM6996I switch */ ++ gpio_direction_output(19, 0); ++} ++ ++int board_early_init_f(void) ++{ ++ gpio_init(); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Lantiq ADM6996I switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device adm6996i_dev = { ++ .name = "adm6996i", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ /* Deactivate reset line of ADM6996I switch */ ++ gpio_set_value(19, 1); ++ ++ /* ADM6996I needs some time to come out of reset */ ++ __udelay(50000); ++ ++ return switch_device_register(&adm6996i_dev); ++} +--- /dev/null ++++ b/board/audiocodes/acmp252/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/audiocodes/acmp252/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x403 ++#define MC_DC08_VALUE 0x103 ++#define MC_DC09_VALUE 0x80B ++#define MC_DC10_VALUE 0x304 ++#define MC_DC11_VALUE 0xD03 ++#define MC_DC12_VALUE 0x2C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x13C ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x402 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1700 ++#define MC_DC22_VALUE 0x1717 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5C ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x2D93 ++#define MC_DC30_VALUE 0x8300 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- a/boards.cfg ++++ b/boards.cfg +@@ -508,6 +508,8 @@ Active mips mips32 danub + Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov ++Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle ++Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck +--- /dev/null ++++ b/include/configs/acmp252.h +@@ -0,0 +1,60 @@ ++/* ++ * Copyright (C) 2013 Daniel Golle ++ * Copyright (C) 2011 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ACMP252" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "AudioCodes MP-252" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_ADM6996I ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0105-MIPS-add-board-support-for-AVM-FritzBox-3370.patch b/package/boot/uboot-lantiq/patches/0105-MIPS-add-board-support-for-AVM-FritzBox-3370.patch new file mode 100644 index 0000000000..77014e44ce --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0105-MIPS-add-board-support-for-AVM-FritzBox-3370.patch @@ -0,0 +1,354 @@ +From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck +Date: Sat, 2 Mar 2013 23:34:00 +0100 +Subject: MIPS: add board support for AVM FritzBox 3370 + +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/board/avm/fb3370/Makefile +@@ -0,0 +1,28 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/avm/fb3370/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/avm/fb3370/ddr_settings.h +@@ -0,0 +1,69 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000100 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x101 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x0 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000300 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401B04 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x0 ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1D445D ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x141F04 ++#define MC_CCR40_VALUE 0x142704 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x0 ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7800301 ++#define MC_CCR58_VALUE 0x7800301 ++#define MC_CCR59_VALUE 0x7800301 ++#define MC_CCR60_VALUE 0x7800301 ++#define MC_CCR61_VALUE 0x4 +--- /dev/null ++++ b/board/avm/fb3370/fb3370.c +@@ -0,0 +1,138 @@ ++/* ++ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_SPL_BUILD) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 0 ++#elif defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#elif defined(CONFIG_SYS_BOOT_NOR) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++static void gpio_init(void) ++{ ++ /* SPI CS 0.4 to serial flash */ ++ gpio_direction_output(10, 1); ++ ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* GPIO 3.0 as input for NAND Ready Busy */ ++ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); ++ /* GPIO 3.1 as output for NAND Read */ ++ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ ++ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ ++ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ ++ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC3: unused */ ++ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ ++ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_addr = 0x80FF0000; ++ ++ ltq_gphy_phy11g_a1x_load(fw_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_addr); ++ ltq_rcu_gphy_boot(1, fw_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++int spi_cs_is_valid(unsigned int bus, unsigned int cs) ++{ ++ if (bus) ++ return 0; ++ ++ if (cs == 4) ++ return 1; ++ ++ return 0; ++} ++ ++void spi_cs_activate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 0); ++ break; ++ default: ++ break; ++ } ++} ++ ++void spi_cs_deactivate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 1); ++ break; ++ default: ++ break; ++ } ++} +--- a/boards.cfg ++++ b/boards.cfg +@@ -517,6 +517,9 @@ Active mips mips32 incai + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk ++Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck ++Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck ++Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck + Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck + Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck + Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck +--- /dev/null ++++ b/include/configs/fb3370.h +@@ -0,0 +1,78 @@ ++/* ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "FB3370" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "AVM FritzBox 3370" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_SPI_FLASH ++#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */ ++ ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH ++ ++#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++#define CONFIG_SPL_SPI_BUS 0 ++#define CONFIG_SPL_SPI_CS 4 ++#define CONFIG_SPL_SPI_MAX_HZ 25000000 ++#define CONFIG_SPL_SPI_MODE 0 ++ ++#define CONFIG_SYS_DRAM_PROBE ++ ++/* Environment */ ++#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS ++#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS ++#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ ++#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE ++ ++#if defined(CONFIG_SYS_BOOT_SFSPL) ++#define CONFIG_ENV_IS_IN_SPI_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++#if defined(CONFIG_SYS_BOOT_EVA) ++#define CONFIG_SYS_TEXT_BASE 0x80100000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_SF \ ++ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_SF ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0106-MIPS-add-board-support-for-Gigaset-SX76X.patch b/package/boot/uboot-lantiq/patches/0106-MIPS-add-board-support-for-Gigaset-SX76X.patch new file mode 100644 index 0000000000..96737fa483 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0106-MIPS-add-board-support-for-Gigaset-SX76X.patch @@ -0,0 +1,247 @@ +From 9e9dec563e4d061e7b34d2d59a89eb05c60f43a7 Mon Sep 17 00:00:00 2001 +From: Luka Perkov +Date: Sat, 2 Mar 2013 23:34:00 +0100 +Subject: MIPS: add board support for Gigaset SX76X + +Signed-off-by: Luka Perkov +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/board/gigaset/sx76x/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/gigaset/sx76x/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/gigaset/sx76x/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x202 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0xF3E ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x300 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA04 ++#define MC_DC21_VALUE 0xF00 ++#define MC_DC22_VALUE 0xF0F ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x63 ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x100 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x514 ++#define MC_DC29_VALUE 0x2D89 ++#define MC_DC30_VALUE 0x8300 ++#define MC_DC31_VALUE 0x2002 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- /dev/null ++++ b/board/gigaset/sx76x/sx76x.c +@@ -0,0 +1,65 @@ ++/* ++ * Copyright (C) 2011 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void gpio_init(void) ++{ ++ /* Activate reset line of ADM6996I switch */ ++ gpio_direction_output(19, 0); ++} ++ ++int board_early_init_f(void) ++{ ++ gpio_init(); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Lantiq ADM6996I switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device adm6996i_dev = { ++ .name = "adm6996i", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ /* Deactivate reset line of ADM6996I switch */ ++ gpio_set_value(19, 1); ++ ++ /* ADM6996I needs some time to come out of reset */ ++ __udelay(50000); ++ ++ return switch_device_register(&adm6996i_dev); ++} +--- a/boards.cfg ++++ b/boards.cfg +@@ -510,6 +510,8 @@ Active mips mips32 danub + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov + Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle + Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle ++Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov ++Active mips mips32 danube gigaset sx76x gigasx76x_ram sx76x:SYS_BOOT_RAM Luka Perkov + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck +--- /dev/null ++++ b/include/configs/sx76x.h +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "GIGASX76X" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Gigaset sx76x" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_ADM6996I ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch b/package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch new file mode 100644 index 0000000000..a1c0bdede0 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch @@ -0,0 +1,301 @@ +From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001 +From: Luka Perkov +Date: Tue, 6 Aug 2013 22:51:00 +0200 +Subject: MIPS: add board support for ZyXEL P-2812HNU-Fx + +Signed-off-by: Luka Perkov + +--- /dev/null ++++ b/board/zyxel/p2812hnufx/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/zyxel/p2812hnufx/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/zyxel/p2812hnufx/ddr_settings.h +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov ++ * ++ * The values have been extracted from original ZyXEL U-Boot. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000100 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x101 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x0 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000300 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401B04 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x0 ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1D445D ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x141F04 ++#define MC_CCR40_VALUE 0x142704 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x0 ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7800301 ++#define MC_CCR58_VALUE 0x7800301 ++#define MC_CCR59_VALUE 0x7800301 ++#define MC_CCR60_VALUE 0x7800301 ++#define MC_CCR61_VALUE 0x4 +--- /dev/null ++++ b/board/zyxel/p2812hnufx/p2812hnufx.c +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_SPL_BUILD) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 0 ++#elif defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++static void gpio_init(void) ++{ ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* GPIO 3.0 as input for NAND Ready Busy */ ++ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); ++ /* GPIO 3.1 as output for NAND Read */ ++ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ ++ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ ++ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ ++ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC3: unused */ ++ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ ++ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_addr = 0x80FF0000; ++ ++ ltq_gphy_phy11g_a1x_load(fw_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_addr); ++ ltq_rcu_gphy_boot(1, fw_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} +--- a/boards.cfg ++++ b/boards.cfg +@@ -527,6 +527,8 @@ Active mips mips32 vrx20 + Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck + Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck + Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck ++Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_nandspl p2812hnufx:SYS_BOOT_NANDSPL Luka Perkov ++Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_ram p2812hnufx:SYS_BOOT_RAM Luka Perkov + Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - + Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - + Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes +--- /dev/null ++++ b/include/configs/p2812hnufx.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "P-2812HNU-Fx" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "ZyXEL P-2812HNU-Fx" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a K9F1G08U0D NAND flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++#define CONFIG_SYS_NAND_PAGE_COUNT 64 ++#define CONFIG_SYS_NAND_PAGE_SIZE 2048 ++#define CONFIG_SYS_NAND_OOBSIZE 64 ++#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) ++#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS ++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 ++ ++#define CONFIG_SYS_DRAM_PROBE ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NANDSPL) ++#define CONFIG_ENV_IS_IN_NAND ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NAND \ ++ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NAND ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0108-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch b/package/boot/uboot-lantiq/patches/0108-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch new file mode 100644 index 0000000000..28632dcb13 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0108-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch @@ -0,0 +1,242 @@ +From fbdbf2ddf2b34d675d53de679c179788b0604c1a Mon Sep 17 00:00:00 2001 +From: Oliver Muth +Date: Sat, 12 Oct 2013 16:49:53 +0200 +Subject: MIPS: add board support for Arcadyan ARV752DPW + +Signed-off-by: Oliver Muth +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/board/arcadyan/arv752dpw/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/arcadyan/arv752dpw/arv752dpw.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (C) 2012 Luka Perkov ++ * Copyright (C) 2013 Oliver Muth ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Realtek rtl8306 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++static struct switch_device rtl8306_dev = { ++ .name = "rtl8306", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&rtl8306_dev); ++} +--- /dev/null ++++ b/board/arcadyan/arv752dpw/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/arv752dpw/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x134 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1400 ++#define MC_DC22_VALUE 0x1414 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5B ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- a/boards.cfg ++++ b/boards.cfg +@@ -508,6 +508,9 @@ Active mips mips32 danub + Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov ++Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN - ++Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR - ++Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM - + Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle + Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle + Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov +--- /dev/null ++++ b/include/configs/arv752dpw.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV752DPW" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_RTL8206 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch b/package/boot/uboot-lantiq/patches/0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch new file mode 100644 index 0000000000..85e3ebdb3a --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch @@ -0,0 +1,244 @@ +From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001 +From: Oliver Muth +Date: Sat, 12 Oct 2013 16:49:53 +0200 +Subject: MIPS: add board support for Arcadyan ARV752DPW22 + +Signed-off-by: Oliver Muth +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/arv752dpw22.c +@@ -0,0 +1,52 @@ ++/* ++ * Copyright (C) 2012 Luka Perkov ++ * Copyright (C) 2013 Oliver Muth ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Atheros ar8216 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device ar8216_dev = { ++ .name = "ar8216", ++ .cpu_port = 0, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&ar8216_dev); ++} +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x134 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1400 ++#define MC_DC22_VALUE 0x1414 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5B ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- a/boards.cfg ++++ b/boards.cfg +@@ -511,6 +511,9 @@ Active mips mips32 danub + Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN - + Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR - + Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM - ++Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN - ++Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR - ++Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM - + Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle + Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle + Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov +--- /dev/null ++++ b/include/configs/arv752dpw22.h +@@ -0,0 +1,68 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV752DPW22" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW22" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_AR8216 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Burnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0110-MIPS-add-board-support-for-Arcadyan-ARV7510PW.patch b/package/boot/uboot-lantiq/patches/0110-MIPS-add-board-support-for-Arcadyan-ARV7510PW.patch new file mode 100644 index 0000000000..8c463685b6 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0110-MIPS-add-board-support-for-Arcadyan-ARV7510PW.patch @@ -0,0 +1,269 @@ +From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001 +From: Matti Laakso +Date: Sat, 2 Mar 2013 23:34:00 +0100 +Subject: MIPS: add board support for Arcadyan ARV7510 + +Signed-off-by: Matti Laakso +Signed-off-by: Daniel Schwierzeck + +--- /dev/null ++++ b/board/arcadyan/arv7510pw/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/arcadyan/arv7510pw/arv7510pw.c +@@ -0,0 +1,72 @@ ++/* ++ * Copyright (C) 2013 Matti Laakso ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void gpio_init(void) ++{ ++ /* Initialize SSIO GPIOs */ ++ gpio_set_altfunc(4, 1, 0, 1); ++ gpio_set_altfunc(5, 1, 0, 1); ++ gpio_set_altfunc(6, 1, 0, 1); ++ ltq_gpio_init(); ++ ++ /* Power led on */ ++ gpio_direction_output(76, 1); ++} ++ ++int board_early_init_f(void) ++{ ++ gpio_init(); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: ADM6996I */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device adm6996i_dev = { ++ .name = "adm6996i", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ /* Deactivate HRST line to release reset of ADM6996I switch */ ++ ltq_reset_once(LTQ_RESET_HARD, 200000); ++ ++ /* ADM6996I needs some time to come out of reset */ ++ __udelay(50000); ++ ++ return switch_device_register(&adm6996i_dev); ++} +--- /dev/null ++++ b/board/arcadyan/arv7510pw/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/arv7510pw/ddr_settings.h +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (C) 2013 Matti Laakso ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x120 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA04 ++#define MC_DC21_VALUE 0x1700 ++#define MC_DC22_VALUE 0x1717 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x52 ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- a/boards.cfg ++++ b/boards.cfg +@@ -505,6 +505,9 @@ Active mips mips32 au1x0 + Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov + Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov + Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov ++Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov ++Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov ++Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov +--- /dev/null ++++ b/include/configs/arv7510pw.h +@@ -0,0 +1,75 @@ ++/* ++ * Copyright (C) 2013 Matti Laakso ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV7510PW" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_ADM6996I ++ ++/* SSIO */ ++#define CONFIG_LTQ_SSIO_SHIFT_REGS ++#define CONFIG_LTQ_SSIO_EDGE_FALLING ++#define CONFIG_LTQ_SSIO_GPHY1_MODE 0 ++#define CONFIG_LTQ_SSIO_GPHY2_MODE 0 ++#define CONFIG_LTQ_SSIO_INIT_VALUE 0 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Buffered write broken in ARV7510PW */ ++#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0060000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0111-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch b/package/boot/uboot-lantiq/patches/0111-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch new file mode 100644 index 0000000000..902a7cfb5e --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0111-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch @@ -0,0 +1,238 @@ +--- /dev/null ++++ b/board/arcadyan/arv7510pw22/arv7510pw22.c +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2014 Álvaro Fernández Rojas ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int board_early_init_f(void) ++{ ++ /* Switch on Power LED */ ++ gpio_direction_output(2, 0); ++ gpio_set_value(2, 0); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Atheros ar8216 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device ar8216_dev = { ++ .name = "ar8216", ++ .cpu_port = 0, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&ar8216_dev); ++} +--- /dev/null ++++ b/board/arcadyan/arv7510pw22/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/arv7510pw22/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2014 Álvaro Fernández Rojas ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x134 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1400 ++#define MC_DC22_VALUE 0x1414 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5B ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- /dev/null ++++ b/board/arcadyan/arv7510pw22/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- a/boards.cfg ++++ b/boards.cfg +@@ -508,6 +508,9 @@ Active mips mips32 danub + Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov + Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov + Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov ++Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_brn arv7510pw22:SYS_BOOT_BRN Álvaro Fernández Rojas ++Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_nor arv7510pw22:SYS_BOOT_NOR Álvaro Fernández Rojas ++Active mips mips32 danube arcadyan arv7510pw22 arv7510pw22_ram arv7510pw22:SYS_BOOT_RAM Álvaro Fernández Rojas + Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov +--- /dev/null ++++ b/include/configs/arv7510pw22.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2014 Álvaro Fernández Rojas ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV7510PW22" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW22" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_AR8216 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Burnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0060000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch b/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch new file mode 100644 index 0000000000..eb688a9caa --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch @@ -0,0 +1,346 @@ +--- /dev/null ++++ b/board/arcadyan/vgv7510kw22/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +--- /dev/null ++++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c +@@ -0,0 +1,136 @@ ++/* ++ * Copyright (C) 2015 Martin Blumenstingl ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_SPL_BUILD) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 0 ++#elif defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#elif defined(CONFIG_SYS_BOOT_NOR) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++#define GPIO_POWER_GREEN 14 ++ ++static void gpio_init(void) ++{ ++ /* SPI CS 0.4 to serial flash */ ++ gpio_direction_output(10, 1); ++ ++ /* Turn on the green power LED */ ++ gpio_direction_output(GPIO_POWER_GREEN, 0); ++ gpio_set_value(GPIO_POWER_GREEN, 0); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* unused */ ++ { 0, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* unused */ ++ { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* Internal GPHY0 with 10/100 firmware for LAN port 2 */ ++ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++ /* Internal GPHY0 with 10/100 firmware for LAN port 1 */ ++ { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++ /* Internal GPHY1 with 10/100 firmware for LAN port 4 */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++ /* Internal GPHY1 with 10/100 firmware for LAN port 3 */ ++ { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_addr = 0x80FF0000; ++ ++ if (ltq_chip_version_get() == 1) ++ ltq_gphy_phy22f_a1x_load(fw_addr); ++ else ++ ltq_gphy_phy22f_a2x_load(fw_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_addr); ++ ltq_rcu_gphy_boot(1, fw_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++int spi_cs_is_valid(unsigned int bus, unsigned int cs) ++{ ++ if (bus) ++ return 0; ++ ++ if (cs == 4) ++ return 1; ++ ++ return 0; ++} ++ ++void spi_cs_activate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 0); ++ break; ++ default: ++ break; ++ } ++} ++ ++void spi_cs_deactivate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 1); ++ break; ++ default: ++ break; ++ } ++} +--- /dev/null ++++ b/board/arcadyan/vgv7510kw22/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +--- /dev/null ++++ b/board/arcadyan/vgv7510kw22/ddr_settings.h +@@ -0,0 +1,71 @@ ++/* ++ * Copyright (C) 2015 Martin Blumenstingl ++ * Based on code by: ++ * Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * and Lantiq Deutschland GmbH ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000100 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x100 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x0 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000401 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401B04 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x0 ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1D445D ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x141F04 ++#define MC_CCR40_VALUE 0x142704 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x0 ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7800301 ++#define MC_CCR58_VALUE 0x7800301 ++#define MC_CCR59_VALUE 0x7800301 ++#define MC_CCR60_VALUE 0x7800301 ++#define MC_CCR61_VALUE 0x4 +--- a/boards.cfg ++++ b/boards.cfg +@@ -531,6 +531,9 @@ Active mips mips32 incai + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk ++Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl ++Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl ++Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl + Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck + Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck + Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck +--- /dev/null ++++ b/include/configs/vgv7510kw22.h +@@ -0,0 +1,78 @@ ++/* ++ * Copyright (C) 2015 Martin Blumenstingl ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "VGV7510KW22" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan VGV7510KW22" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPI_FLASH ++#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29GL128EL parallel flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++#define CONFIG_SPL_SPI_BUS 0 ++#define CONFIG_SPL_SPI_CS 4 ++#define CONFIG_SPL_SPI_MAX_HZ 25000000 ++#define CONFIG_SPL_SPI_MODE 0 ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ ++ ++#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */ ++ ++/* Environment */ ++#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS ++#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS ++#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ ++#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE ++ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_IS_NOWHERE ++#elif defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (384 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (128 * 1024) ++ ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ "kernel_addr=0xB0080000\0" ++ ++#endif /* __CONFIG_H */ diff --git a/package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch b/package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch new file mode 100644 index 0000000000..e68ce2d31a --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch @@ -0,0 +1,239 @@ +--- /dev/null ++++ b/board/arcadyan/arv8539pw22/Makefile +@@ -0,0 +1,28 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### ++ +--- /dev/null ++++ b/board/arcadyan/arv8539pw22/arv8539pw22.c +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (C) 2012 Luka Perkov ++ * Copyright (C) 2013 Oliver Muth ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Atheros ar8216 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device ar8216_dev = { ++ .name = "ar8216", ++ .cpu_port = 0, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&ar8216_dev); ++} ++ +--- /dev/null ++++ b/board/arcadyan/arv8539pw22/config.mk +@@ -0,0 +1,8 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) ++ +--- /dev/null ++++ b/board/arcadyan/arv8539pw22/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x134 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1400 ++#define MC_DC22_VALUE 0x1414 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5B ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +--- a/boards.cfg ++++ b/boards.cfg +@@ -520,6 +520,9 @@ Active mips mips32 danub + Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN - + Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR - + Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM - ++Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_brn arv8539pw22:SYS_BOOT_BRN - ++Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_nor arv8539pw22:SYS_BOOT_NOR - ++Active mips mips32 danube arcadyan arv8539pw22 arv8539pw22_ram arv8539pw22:SYS_BOOT_RAM - + Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle + Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle + Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov +--- /dev/null ++++ b/include/configs/arv8539pw22.h +@@ -0,0 +1,68 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV8539PW22" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Speedport W 504V Typ A" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_AR8216 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Burnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyS1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include ++#include ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ -- cgit v1.2.3