% Generated using the yosys 'help -write-tex-command-reference-manual' command.
\section{abc -- use ABC for technology mapping}
\label{cmd:abc}
\begin{lstlisting}[numbers=left,frame=single]
abc [options] [selection]
This pass uses the ABC tool [1] for technology mapping of yosys's internal gate
library to a target architecture.
-exe <command>
use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
This can e.g. be used to call a specific version of ABC or a wrapper.
-script <file>
use the specified ABC script file instead of the default script.
if <file> starts with a plus sign (+), then the rest of the filename
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.
if no -script parameter is given, the following scripts are used:
for -liberty without -constr:
strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
&nf {D}; &put
for -liberty with -constr:
strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
&nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p
for -lut/-luts (only one LUT size):
strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2;
lutpack {S}
for -lut/-luts (different LUT sizes):
strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2
for -sop:
strash; ifraig; scorr; dc2; dretime; strash; dch -f;
cover {I} {P}
otherwise:
strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
&nf {D}; &put
-fast
use different default scripts that are slightly faster (at the cost
of output quality):
for -liberty without -constr:
strash; dretime; map {D}
for -liberty with -constr:
strash; dretime; map {D}; buffer; upsize {D}; dnsize {D};
stime -p
for -lut/-luts:
strash; dretime; if
for -sop:
strash; dretime; cover -I {I} -P {P}
otherwise:
strash; dretime; map
-liberty <file>
generate netlists for the specified cell library (using the liberty
file format).
-constr <file>
pass this file with timing constraints to ABC. use with -liberty.
a constr file contains two lines:
set_driving_cell <cell_name>
set_load <floating_point_number>
the set_driving_cell statement defines which cell type is assumed to
drive the primary inputs and the set_load statement sets the load in
femtofarads for each primary output.
-D <picoseconds>
set delay target. the string {D} in the default scripts above is
replaced by this option when used, and an empty string otherwise.
this also replaces 'dretime' with 'dretime; retime -o {D}' in the
default scripts above.
-I <num>
maximum number of SOP inputs.
(replaces {I} in the default scripts above)
-P <num>
maximum number of SOP products.
(replaces {P} in the default scripts above)
-S <num>
maximum number of LUT inputs shared.
(replaces {S} in the default scripts above, default: -S 1)
-lut <width>
generate netlist using luts of (max) the specified width.
-lut <w1>:<w2>
generate netlist using luts of (max) the specified width <w2>. All
luts with width <= <w1> have constant cost. for luts larger than <w1>
the area cost doubles with each additional input bit. the delay cost
is still constant for all lut widths.
-luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
generate netlist using luts. Use the specified costs for luts with 1,
2, 3, .. inputs.
-sop
map to sum-of-product cells and inverters
-g type1,type2,...
Map to the specified list of gate types. Supported gates types are:
AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,
NMUX, AOI3, OAI3, AOI4, OAI4.
(The NOT gate is always added to this list automatically.)
The following aliases can be used to reference common sets of gate types:
simple: AND OR XOR MUX
cmos2: NAND NOR
cmos3: NAND NOR AOI3 OAI3
cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4
cmos: NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR
gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT
aig: AND NAND OR NOR ANDNOT ORNOT
The alias 'all' represent the full set of all gate types.
Prefix a gate type with a '-' to remove it from the list. For example
the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.
The default is 'all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4'.
-dff
also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
clock domains are automatically partitioned in clock domains and each
domain is passed through ABC independently.
-clk [!]<clock-signal-name>[,[!]<enable-signal-name>]
use only the specified clock domain. this is like -dff, but only FF
cells that belong to the specified clock domain are used.
-keepff
set the "keep" attribute on flip-flop output wires. (and thus preserve
them, for example for equivalence checking.)
-nocleanup
when this option is used, the temporary files created by this pass
are not removed. this is useful for debugging.
-showtmp
print the temp dir name in log. usually this is suppressed so that the
command output is identical across runs.
-markgroups
set a 'abcgroup' attribute on all objects created by ABC. The value of
this attribute is a unique integer for each ABC process started. This
is useful for debugging the partitioning of clock domains.
-dress
run the 'dress' command after all other ABC commands. This aims to
preserve naming by an equivalence check between the original and post-ABC
netlists (experimental).
When neither -liberty nor -lut is used, the Yosys standard cell library is
loaded into ABC before the ABC script is executed.
Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write_blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.
[1] http://www.eecs.berkeley.edu/~alanmi/abc/
\end{lstlisting}
\section{abc9 -- use ABC9 for technology mapping}
\label{cmd:abc9}
\begin{lstlisting}[numbers=left,frame=single]
abc9 [options] [selection]
This script pass performs a sequence of commands to facilitate the use of the ABC
tool [1] for technology mapping of the current design to a target FPGA
architecture. Only fully-selected modules are supported.
-run <from_label>:<to_label>
only run the commands between the labels (see below). an empty
from label is synonymous to 'begin', and empty to label is
synonymous to the end of the command list.
-exe <command>
use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
This can e.g. be used to call a specific version of ABC or a wrapper.
-script <file>
use the specified ABC script file instead of the default script.
if <file> starts with a plus sign (+), then the rest of the filename
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.
if no -script parameter is given, the following scripts are used:
&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs
-fast
use different default scripts that are slightly faster (at the cost
of output quality):
&if {C} {W} {D} {R} -v
-D <picoseconds>
set delay target. the string {D} in the default scripts above is
replaced by this option when used, and an empty string otherwise
(indicating best possible delay).
-lut <width>
generate netlist using luts of (max) the specified width.
-lut <w1>:<w2>
generate netlist using luts of (max) the specified width <w2>. All
luts with width <= <w1> have constant cost. for luts larger than <w1>
the area cost doubles with each additional input bit. the delay cost
is still constant for all lut widths.
-lut <file>
pass this file with lut library to ABC.
-luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
generate netlist using luts. Use the specified costs for luts with 1,
2, 3, .. inputs.
-maxlut <width>
when auto-generating the lut library, discard all luts equal to or
greater than this size (applicable when neither -lut nor -luts is
specified).
-dff
also pass $_ABC9_FF_ cells through to ABC. modules with many clock
domains are marked as such and automatically partitioned by ABC.
-nocleanup
when this option is used, the temporary files created by this pass
are not removed. this is useful for debugging.
-showtmp
print the temp dir name in log. usually this is suppressed so that the
command output is identical across runs.
-box <file>
pass this file with box library to ABC.
Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as an XAIGER file with `write_xaiger' and then load that into ABC
externally if you want to use ABC to convert your design into another format.
[1] http://www.eecs.berkeley.edu/~alanmi/abc/
pre:
abc9_ops -check
scc -set_attr abc9_scc_id {}
abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff] (option for -dff)
abc9_ops -prep_lut <maxlut> (skip if -lut or -luts)
abc9_ops -prep_box [-dff] (skip if -box)
select -set abc9_holes A:abc9_holes
flatten -wb @abc9_holes
techmap @abc9_holes
abc9_ops -prep_dff (only if -dff)
opt -purge @abc9_holes
aigmap
wbflip @abc9_holes
map:
foreach module in selection
abc9_ops -write_lut <abc-temp-dir>/input.lut (skip if '-lut' or '-luts')
abc9_ops -write_box <abc-temp-dir>/input.box
write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig
abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box
read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig
abc9_ops -reintegrate
\end{lstlisting}
\section{abc9\_exe -- use ABC9 for technology mapping}
\label{cmd:abc9_exe}
\begin{lstlisting}[numbers=left,frame=single]
abc9_exe [options]
This pass uses the ABC tool [1] for technology mapping of the top module
(according to the (* top *) attribute or if only one module is currently selected)
to a target FPGA architecture.
-exe <command>
use the specified command instead of "<yosys-bindir>/yosys-abc" to execute ABC.
This can e.g. be used to call a specific version of ABC or a wrapper.
-script <file>
use the specified ABC script file instead of the default script.
if <file> starts with a plus sign (+), then the rest of the filename
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.
if no -script parameter is given, the following scripts are used:
&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs
-fast
use different default scripts that are slightly faster (at the cost
of output quality):
&if {C} {W} {D} {R} -v
-D <picoseconds>
set delay target. the string {D} in the default scripts above is
replaced by this option when used, and an empty string otherwise
(indicating best possible delay).
-lut <width>
generate netlist using luts of (max) the specified width.
-lut <w1>:<w2>
generate netlist using luts of (max) the specified width <w2>. All
luts with width <= <w1> have constant cost. for luts larger than <w1>
the area cost doubles with each additional input bit. the delay cost
is still constant for all lut widths.
-lut <file>
pass this file with lut library to ABC.
-luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
generate netlist using luts. Use the specified costs for luts with 1,
2, 3, .. inputs.
-showtmp
print the temp dir name in log. usually this is suppressed so that the
command output is identical across runs.
-box <file>
pass this file with box library to ABC.
-cwd <dir>
use this as the current working directory, inside which the 'input.xaig'
file is expected. temporary files will be created in this directory, and
the mapped result will be written to 'output.aig'.
Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write_blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.
[1] http://www.eecs.berkeley.edu/~alanmi/abc/
\end{lstlisting}
\section{abc9\_ops -- helper functions for ABC9}
\label{cmd:abc9_ops}
\begin{lstlisting}[numbers=left,frame=single]
abc9_ops [options] [selection]
This pass contains a set of supporting operations for use during ABC technology
mapping, and is expected to be called in conjunction with other operations from
the `abc9' script pass. Only fully-selected modules are supported.
-check
check that the design is valid, e.g. (* abc9_box_id *) values are unique,
(* abc9_carry *) is only given for one input/output port, etc.
-prep_delays
insert `$__ABC9_DELAY' blackbox cells into the design to account for
certain required times.
-mark_scc
for an arbitrarily chosen cell in each unique SCC of each selected module
(tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all
wires driven by this cell's outputs with a (* keep *) attribute in order
to break the SCC. this temporary attribute will be removed on -reintegrate.
-prep_xaiger
prepare the design for XAIGER output. this includes computing the
topological ordering of ABC9 boxes, as well as preparing the
'<module-name>$holes' module that contains the logic behaviour of ABC9
whiteboxes.
-dff
consider flop cells (those instantiating modules marked with (* abc9_flop *))
during -prep_{delays,xaiger,box}.
-prep_dff
compute the clock domain and initial value of each flop in the design.
process the '$holes' module to support clock-enable functionality.
-prep_lut <maxlut>
pre-compute the lut library by analysing all modules marked with
(* abc9_lut=<area> *).
