From d9eefa7a7031543571d434693c7f984dfbdc990d Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 2 Aug 2018 08:44:29 +0200 Subject: mac80211: rebase ontop of v4.18.5 Signed-off-by: John Crispin --- .../544-ath9k-ar933x-usb-hang-workaround.patch | 79 ---------------------- 1 file changed, 79 deletions(-) delete mode 100644 package/kernel/mac80211/patches/544-ath9k-ar933x-usb-hang-workaround.patch (limited to 'package/kernel/mac80211/patches/544-ath9k-ar933x-usb-hang-workaround.patch') diff --git a/package/kernel/mac80211/patches/544-ath9k-ar933x-usb-hang-workaround.patch b/package/kernel/mac80211/patches/544-ath9k-ar933x-usb-hang-workaround.patch deleted file mode 100644 index 680bb6d590..0000000000 --- a/package/kernel/mac80211/patches/544-ath9k-ar933x-usb-hang-workaround.patch +++ /dev/null @@ -1,79 +0,0 @@ ---- a/drivers/net/wireless/ath/ath9k/hw.c -+++ b/drivers/net/wireless/ath/ath9k/hw.c -@@ -246,6 +246,19 @@ void ath9k_hw_get_channel_centers(struct - centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); - } - -+static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah) -+{ -+ /* On AR9330 and AR9340 devices, some PHY registers must be -+ * tuned to gain better stability/performance. These registers -+ * might be changed while doing wlan reset so the registers must -+ * be reprogrammed after each reset. -+ */ -+ REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20)); -+ REG_RMW(ah, AR_PHY_USB_CTRL2, -+ (1 << 21) | (0xf << 22), -+ (1 << 21) | (0x3 << 22)); -+} -+ - /******************/ - /* Chip Revisions */ - /******************/ -@@ -1414,6 +1427,9 @@ static bool ath9k_hw_set_reset(struct at - udelay(50); - } - -+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) -+ ath9k_hw_disable_pll_lock_detect(ah); -+ - return true; - } - -@@ -1513,6 +1529,9 @@ static bool ath9k_hw_chip_reset(struct a - ar9003_hw_internal_regulator_apply(ah); - ath9k_hw_init_pll(ah, chan); - -+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) -+ ath9k_hw_disable_pll_lock_detect(ah); -+ - return true; - } - -@@ -1820,8 +1839,14 @@ static int ath9k_hw_do_fastcc(struct ath - if (AR_SREV_9271(ah)) - ar9002_hw_load_ani_reg(ah, chan); - -+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) -+ ath9k_hw_disable_pll_lock_detect(ah); -+ - return 0; - fail: -+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) -+ ath9k_hw_disable_pll_lock_detect(ah); -+ - return -EINVAL; - } - -@@ -2075,6 +2100,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st - ath9k_hw_set_radar_params(ah); - } - -+ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) -+ ath9k_hw_disable_pll_lock_detect(ah); -+ - return 0; - } - EXPORT_SYMBOL(ath9k_hw_reset); ---- a/drivers/net/wireless/ath/ath9k/phy.h -+++ b/drivers/net/wireless/ath/ath9k/phy.h -@@ -48,6 +48,9 @@ - #define AR_PHY_PLL_CONTROL 0x16180 - #define AR_PHY_PLL_MODE 0x16184 - -+#define AR_PHY_USB_CTRL1 0x16c84 -+#define AR_PHY_USB_CTRL2 0x16c88 -+ - enum ath9k_ant_div_comb_lna_conf { - ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, - ATH_ANT_DIV_COMB_LNA2, -- cgit v1.2.3