From b5073ca2c859fe8763a0717abcfb5f5646d5a543 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 14 Apr 2015 12:17:34 +0000 Subject: mac80211: merge a number of upstream driver fixes/improvements Signed-off-by: Felix Fietkau SVN-Revision: 45432 --- .../327-ath9k-ath9k_hw_loadnf-use-REG_RMW.patch | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 package/kernel/mac80211/patches/327-ath9k-ath9k_hw_loadnf-use-REG_RMW.patch (limited to 'package/kernel/mac80211/patches/327-ath9k-ath9k_hw_loadnf-use-REG_RMW.patch') diff --git a/package/kernel/mac80211/patches/327-ath9k-ath9k_hw_loadnf-use-REG_RMW.patch b/package/kernel/mac80211/patches/327-ath9k-ath9k_hw_loadnf-use-REG_RMW.patch new file mode 100644 index 0000000000..e5a362ffa6 --- /dev/null +++ b/package/kernel/mac80211/patches/327-ath9k-ath9k_hw_loadnf-use-REG_RMW.patch @@ -0,0 +1,71 @@ +From: Oleksij Rempel +Date: Sun, 22 Mar 2015 19:29:54 +0100 +Subject: [PATCH] ath9k: ath9k_hw_loadnf: use REG_RMW + +Signed-off-by: Oleksij Rempel +Signed-off-by: Kalle Valo +--- + +--- a/drivers/net/wireless/ath/ath9k/calib.c ++++ b/drivers/net/wireless/ath/ath9k/calib.c +@@ -238,7 +238,6 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s + { + struct ath9k_nfcal_hist *h = NULL; + unsigned i, j; +- int32_t val; + u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask; + struct ath_common *common = ath9k_hw_common(ah); + s16 default_nf = ath9k_hw_get_default_nf(ah, chan); +@@ -246,6 +245,7 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s + if (ah->caldata) + h = ah->caldata->nfCalHist; + ++ ENABLE_REG_RMW_BUFFER(ah); + for (i = 0; i < NUM_NF_READINGS; i++) { + if (chainmask & (1 << i)) { + s16 nfval; +@@ -258,10 +258,8 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s + else + nfval = default_nf; + +- val = REG_READ(ah, ah->nf_regs[i]); +- val &= 0xFFFFFE00; +- val |= (((u32) nfval << 1) & 0x1ff); +- REG_WRITE(ah, ah->nf_regs[i], val); ++ REG_RMW(ah, ah->nf_regs[i], ++ (((u32) nfval << 1) & 0x1ff), 0x1ff); + } + } + +@@ -274,6 +272,7 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, + AR_PHY_AGC_CONTROL_NO_UPDATE_NF); + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); ++ REG_RMW_BUFFER_FLUSH(ah); + + /* + * Wait for load to complete, should be fast, a few 10s of us. +@@ -309,19 +308,17 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s + * by the median we just loaded. This will be initial (and max) value + * of next noise floor calibration the baseband does. + */ +- ENABLE_REGWRITE_BUFFER(ah); ++ ENABLE_REG_RMW_BUFFER(ah); + for (i = 0; i < NUM_NF_READINGS; i++) { + if (chainmask & (1 << i)) { + if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan)) + continue; + +- val = REG_READ(ah, ah->nf_regs[i]); +- val &= 0xFFFFFE00; +- val |= (((u32) (-50) << 1) & 0x1ff); +- REG_WRITE(ah, ah->nf_regs[i], val); ++ REG_RMW(ah, ah->nf_regs[i], ++ (((u32) (-50) << 1) & 0x1ff), 0x1ff); + } + } +- REGWRITE_BUFFER_FLUSH(ah); ++ REG_RMW_BUFFER_FLUSH(ah); + + return 0; + } -- cgit v1.2.3