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/*
* Binary translate privilege-sensitive ops to privileged
*
* Copyright (C) 2004 Hewlett-Packard Co.
* Dan Magenheimer (dan.magenheimer@hp.com)
*
*/
#include "privify.h"
typedef unsigned long long u64;
typedef unsigned long long IA64_INST;
typedef union U_IA64_BUNDLE {
u64 i64[2];
struct { u64 template:5,slot0:41,slot1a:18,slot1b:23,slot2:41; };
// NOTE: following doesn't work because bitfields can't cross natural
// size boundaries
//struct { u64 template:5, slot0:41, slot1:41, slot2:41; };
} IA64_BUNDLE;
typedef enum E_IA64_SLOT_TYPE { I, M, F, B, L, ILLEGAL } IA64_SLOT_TYPE;
typedef union U_INST64_A5 {
IA64_INST inst;
struct { u64 qp:6, r1:7, imm7b:7, r3:2, imm5c:5, imm9d:9, s:1, major:4; };
} INST64_A5;
typedef union U_INST64_B4 {
IA64_INST inst;
struct { u64 qp:6, btype:3, un3:3, p:1, b2:3, un11:11, x6:6, wh:2, d:1, un1:1, major:4; };
} INST64_B4;
typedef union U_INST64_B8 {
IA64_INST inst;
struct { u64 qp:6, un21:21, x6:6, un4:4, major:4; };
} INST64_B8;
typedef union U_INST64_B9 {
IA64_INST inst;
struct { u64 qp:6, imm20:20, :1, x6:6, :3, i:1, major:4; };
} INST64_B9;
typedef union U_INST64_I19 {
IA64_INST inst;
struct { u64 qp:6, imm20:20, :1, x6:6, x3:3, i:1, major:4; };
} INST64_I19;
typedef union U_INST64_I26 {
IA64_INST inst;
struct { u64 qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4;};
} INST64_I26;
typedef union U_INST64_I27 {
IA64_INST inst;
struct { u64 qp:6, :7, imm:7, ar3:7, x6:6, x3:3, s:1, major:4;};
} INST64_I27;
typedef union U_INST64_I28 { // not privileged (mov from AR)
IA64_INST inst;
struct { u64 qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4;};
} INST64_I28;
typedef union U_INST64_M28 {
IA64_INST inst;
struct { u64 qp:6, :14, r3:7, x6:6, x3:3, :1, major:4;};
} INST64_M28;
typedef union U_INST64_M29 {
IA64_INST inst;
struct { u64 qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4;};
} INST64_M29;
typedef union U_INST64_M30 {
IA64_INST inst;
struct { u64 qp:6, :7, imm:7, ar3:7,x4:4,x2:2,x3:3,s:1,major:4;};
} INST64_M30;
typedef union U_INST64_M31 {
IA64_INST inst;
struct { u64 qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4;};
} INST64_M31;
typedef union U_INST64_M32 {
IA64_INST inst;
struct { u64 qp:6, :7, r2:7, cr3:7, x6:6, x3:3, :1, major:4;};
} INST64_M32;
typedef union U_INST64_M33 {
IA64_INST inst;
struct { u64 qp:6, r1:7, :7, cr3:7, x6:6, x3:3, :1, major:4; };
} INST64_M33;
typedef union U_INST64_M35 {
IA64_INST inst;
struct { u64 qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; };
} INST64_M35;
typedef union U_INST64_M36 {
IA64_INST inst;
struct { u64 qp:6, r1:7, :14, x6:6, x3:3, :1, major:4; };
} INST64_M36;
typedef union U_INST64_M41 {
IA64_INST inst;
struct { u64 qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; };
} INST64_M41;
typedef union U_INST64_M42 {
IA64_INST inst;
struct { u64 qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; };
} INST64_M42;
typedef union U_INST64_M43 {
IA64_INST inst;
struct { u64 qp:6, r1:7, :7, r3:7, x6:6, x3:3, :1, major:4; };
} INST64_M43;
typedef union U_INST64_M44 {
IA64_INST inst;
struct { u64 qp:6, imm:21, x4:4, i2:2, x3:3, i:1, major:4; };
} INST64_M44;
typedef union U_INST64_M45 {
IA64_INST inst;
struct { u64 qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; };
} INST64_M45;
typedef union U_INST64_M46 {
IA64_INST inst;
struct { u64 qp:6, r1:7, un7:7, r3:7, x6:6, x3:3, un1:1, major:4; };
} INST64_M46;
typedef union U_INST64 {
IA64_INST inst;
struct { u64 :37, major:4; } generic;
INST64_A5 A5; // used in build_hypercall_bundle only
INST64_B4 B4; // used in build_hypercall_bundle only
INST64_B8 B8; // rfi, bsw.[01]
INST64_B9 B9; // break.b
INST64_I19 I19; // used in build_hypercall_bundle only
INST64_I26 I26; // mov register to ar (I unit)
INST64_I27 I27; // mov immediate to ar (I unit)
INST64_I28 I28; // mov from ar (I unit)
INST64_M28 M28; // purge translation cache entry
INST64_M29 M29; // mov register to ar (M unit)
INST64_M30 M30; // mov immediate to ar (M unit)
INST64_M31 M31; // mov from ar (M unit)
INST64_M32 M32; // mov reg to cr
INST64_M33 M33; // mov from cr
INST64_M35 M35; // mov to psr
INST64_M36 M36; // mov from psr
INST64_M41 M41; // translation cache insert
INST64_M42 M42; // mov to indirect reg/translation reg insert
INST64_M43 M43; // mov from indirect reg
INST64_M44 M44; // set/reset system mask
INST64_M45 M45; // translation purge
INST64_M46 M46; // translation access (tpa,tak)
} INST64;
#define MASK_41 ((u64)0x1ffffffffff)
long priv_verbose = 0;
#define verbose(a...) do { if (priv_verbose) printf(a); } while(0)
/*
* privify_inst
*
* Replaces privilege-sensitive instructions (and reads from write-trapping
* registers) with privileged/trapping instructions as follows:
* mov rx=ar.cflg -> mov ar.cflg=r(x+64) [**]
* mov rx=ar.ky -> mov ar.ky=r(x+64)
* fc rx -> ptc r(x+64)
* thash rx=ry -> tak rx=r(y+64)
* ttag rx=ry -> tpa rx=r(y+64)
* mov rx=cpuid[ry] -> mov r(x+64)=rr[ry]
* mov rx=pmd[ry] -> mov r(x+64)=pmc[ry] [**]
* cover -> break.b 0x1fffff
*
* [**] not currently implemented
*/
IA64_INST privify_inst(IA64_INST inst_val,
IA64_SLOT_TYPE slot_type, IA64_BUNDLE *bp, char **msg)
{
INST64 inst = *(INST64 *)&inst_val;
*msg = 0;
switch (slot_type) {
case M:
// FIXME: Also use for mov_to/from_ar.cflag (M29/M30) (IA32 only)
if (inst.generic.major != 1) break;
if (inst.M46.x3 != 0) break;
if (inst.M31.x6 == 0x22 && inst.M31.ar3 < 8) {
// mov r1=kr -> mov kr=r1+64
verbose("privify_inst: privified mov r1=kr @%p\n",bp);
if (inst.M31.r1 >= 64) *msg = "mov r1=kr w/r1>63";
else privify_mov_from_kr_m(inst);
break;
}
if (inst.M29.x6 == 0x2a && inst.M29.ar3 < 8) {// mov kr=r1
if (inst.M29.r2 >= 64) *msg = "mov kr=r2 w/r2>63";
break;
}
if (inst.M28.x6 == 0x30) {
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