From 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 Mon Sep 17 00:00:00 2001 From: Yutang Jiang Date: Sat, 29 Oct 2016 00:18:23 +0800 Subject: layerscape: add 64b/32b target for ls1012ardb device The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang --- ...scale-ls1012afrdm-Add-support-of-Ethernet.patch | 155 +++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch (limited to 'package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch') diff --git a/package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch b/package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch new file mode 100644 index 0000000000..0b993cb6a8 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0045-board-freescale-ls1012afrdm-Add-support-of-Ethernet.patch @@ -0,0 +1,155 @@ +From 691deae097b2583a4e9890307c684ce9f58aca78 Mon Sep 17 00:00:00 2001 +From: Prabhakar Kushwaha +Date: Tue, 24 May 2016 15:03:33 +0530 +Subject: [PATCH 45/93] board/freescale/ls1012afrdm: Add support of Ethernet + +Add support of SGMII Ethernet present on FRDM board. +Also add support of PHY reset. + +Signed-off-by: Prabhakar Kushwaha +--- + board/freescale/ls1012afrdm/Makefile | 1 + + board/freescale/ls1012afrdm/eth.c | 86 +++++++++++++++++++++++++++++ + board/freescale/ls1012afrdm/ls1012afrdm.c | 5 -- + include/configs/ls1012afrdm.h | 5 ++ + 4 files changed, 92 insertions(+), 5 deletions(-) + create mode 100644 board/freescale/ls1012afrdm/eth.c + +diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile +index dbfa2ce..1364f22 100644 +--- a/board/freescale/ls1012afrdm/Makefile ++++ b/board/freescale/ls1012afrdm/Makefile +@@ -5,3 +5,4 @@ + # + + obj-y += ls1012afrdm.o ++obj-y += eth.o +diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c +new file mode 100644 +index 0000000..8ae3f45 +--- /dev/null ++++ b/board/freescale/ls1012afrdm/eth.c +@@ -0,0 +1,86 @@ ++/* ++ * Copyright 2016 Freescale Semiconductor, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../../../drivers/net/pfe_eth/pfe_eth.h" ++#include ++ ++#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" ++ ++#define MASK_ETH_PHY_RST 0x00000100 ++ ++void reset_phy(void) ++{ ++ unsigned int val; ++ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_GPIO1_ADDR); ++ ++ setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); ++ ++ val = in_be32(&pgpio->gpdat); ++ setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); ++ mdelay(10); ++ ++ val = in_be32(&pgpio->gpdat); ++ setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST); ++ mdelay(50); ++} ++ ++int board_eth_init(bd_t *bis) ++{ ++#ifdef CONFIG_FSL_PPFE ++ struct mii_dev *bus; ++ struct mdio_info mac1_mdio_info; ++ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; ++ ++ ++ /*TODO Following config should be done for all boards, where is the right place to put this */ ++ out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0); ++ out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0); ++ ++ /*CCI-400 QoS settings for PFE */ ++ out_be32(&scfg->wr_qos1, 0x0ff00000); ++ out_be32(&scfg->rd_qos1, 0x0ff00000); ++ ++ /* Set RGMII into 1G + Full duplex mode */ ++ out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD)); ++ ++ ++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF); ++ out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF); ++ ++ mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/ ++ mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME; ++ ++ bus = ls1012a_mdio_init(&mac1_mdio_info); ++ if(!bus) ++ { ++ printf("Failed to register mdio \n"); ++ return -1; ++ } ++ ++ /*MAC1 */ ++ ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); ++ ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); ++ ++ /*MAC2 */ ++ ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); ++ ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII); ++ ++ ++ cpu_eth_init(bis); ++#endif ++ return pci_eth_init(bis); ++} +diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c +index 6be8951..6856250 100644 +--- a/board/freescale/ls1012afrdm/ls1012afrdm.c ++++ b/board/freescale/ls1012afrdm/ls1012afrdm.c +@@ -133,11 +133,6 @@ int dram_init(void) + return 0; + } + +-int board_eth_init(bd_t *bis) +-{ +- return pci_eth_init(bis); +-} +- + int board_early_init_f(void) + { + fsl_lsch2_early_init_f(); +diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h +index 3231ab7..5e619c1 100644 +--- a/include/configs/ls1012afrdm.h ++++ b/include/configs/ls1012afrdm.h +@@ -18,8 +18,13 @@ + #define CONFIG_SYS_MEMTEST_START 0x80000000 + #define CONFIG_SYS_MEMTEST_END 0x9fffffff + ++#ifdef CONFIG_FSL_PPFE ++#define EMAC1_PHY_ADDR 0x2 ++#define EMAC2_PHY_ADDR 0x1 + #define CONFIG_PHYLIB + #define CONFIG_PHY_REALTEK ++#define CONFIG_RESET_PHY_R ++#endif + /* + * USB + */ +-- +1.7.9.5 + -- cgit v1.2.3