From cf50f720695eb2d9d232a588b5a7f4959ef3fcee Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sun, 12 Aug 2018 21:13:31 +0800 Subject: ath79: ar913x: fix eth pll register PLL for eth0 internal clock on ar913x is at 0x18050014 and AR913X_ETH0_PLL_SHIFT is 20 instead of 17 Signed-off-by: Chuanhong Guo --- target/linux/ath79/dts/ar9132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ath79/dts/ar9132.dtsi b/target/linux/ath79/dts/ar9132.dtsi index 01572c022e..9d8ddcf9ba 100644 --- a/target/linux/ath79/dts/ar9132.dtsi +++ b/target/linux/ath79/dts/ar9132.dtsi @@ -189,7 +189,7 @@ reg = <0x19000000 0x200 0x18070000 0x4>; pll-data = <0x1a000000 0x13000a44 0x00441099>; - pll-reg = <0x4 0x10 17>; + pll-reg = <0x4 0x14 20>; pll-handle = <&pll>; resets = <&rst 9>; reset-names = "mac"; -- cgit v1.2.3