| Commit message (Collapse) | Author | Age | Files | Lines |
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SVN-Revision: 33726
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SVN-Revision: 33725
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Properly terminate the correct platform resource for laguna UARTs
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33721
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level monitoring and control of Gateworks boards. It is used on several product families spanning several different target architectures (ixp4xx, cns3xxx, davinci).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33720
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Resolves crashes when probing multiple serial devices
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33719
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Useful for loading the kernel into RAM using ADAM2/PSPBoot.
SVN-Revision: 33718
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Keep fq_codel flow state around after queue empty.
SVN-Revision: 33687
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Bugfix from linux head - don't delay acks from ECN congestion
experienced in some situations.
SVN-Revision: 33686
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The Laguna boards do not use all the same pins for SDHCI as the Cavium
reference board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33684
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The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too. I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.
This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33683
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This allows sysupgrade for devices such as the Gateworks Avila/Cambria
product families based on the ixp4xx using the redboot bootloader with
combined FIS directory and RedBoot config partitions on larger FLASH
devices with larger eraseblocks.
This second iteration of this patch addresses previous issues:
- whitespace breakage fixed
- unlock in all scenarios
- simplification and fix logic bug
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33681
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Enabling OPTIMIZE_FOR_SIZE cuts the kernel binary down by 50K which is
critical for some small-footprint boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33679
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SVN-Revision: 33672
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SVN-Revision: 33671
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Fixes #12292.
SVN-Revision: 33670
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it's a 6328, not a 6348.
SVN-Revision: 33665
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Since there is only one user of bcm_tag.h left, we can safely move it
into the firmware-utils directory, replacing the symlink.
SVN-Revision: 33655
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gpio_keys_polled needs to be loaded in preinit for buttons to work for
entering failsafe.
SVN-Revision: 33653
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/base-files/lib/cns3xxx.sh | 22 ++
target/linux/cns3xxx/base-files/lib/upgrade/platform.sh | 122 ++++++++++++++++
target/linux/cns3xxx/image/Makefile | 19 +-
3 files changed, 159 insertions(+), 4 deletions(-)
SVN-Revision: 33650
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Add GPIO/LED support for Gateworks GW2383
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/patches-3.3/300-laguna_support.patch | 18 +++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
SVN-Revision: 33649
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/patches-3.3/470-gpio_irq.patch | 536 ++++++++++++++++++++
1 file changed, 536 insertions(+)
SVN-Revision: 33648
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Several new features for newer boards:
- add additional UARTs present on some boards
- add additional LEDs present on some boards
- add HSS audio device codec present on some boards
- add support for GSC present on some boards
- add per model setup support for newer boards
- set FLASH window per-model for boards with larger FLASH
Some fixes:
- add IRQ mapping for additional PCI devices (USB Host)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33647
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roll all avila patches into a single patch (no code changes)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33646
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Add ixp4xx HSS audio driver for Avila
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33645
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Several new features for newer boards:
- add irq mapping for additional devices
- add platform data for i2c bus to SFP modules
- add additional UARTs present on some boards
- increased R/W delay for expansion bus UARTs
- add additional LEDs present on some boards
- add GPIO exports and configuration
- add ENET switch config present on some boards
- add support for GSC present on some boards
- added per model setup support for newer boards
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33644
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roll all cambria patches into a single patch (no code changes)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33643
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This is being done for general cleanup
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33642
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SVN-Revision: 33641
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SVN-Revision: 33640
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SVN-Revision: 33639
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SVN-Revision: 33638
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SVN-Revision: 33623
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SVN-Revision: 33622
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SVN-Revision: 33621
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Before it was tried to initialize the deactivated PCIe core in client
mode, but this causes the SoC to hang. Just do not initialize it at all
and ignore the core it is not working and nothing is connected to it
when the specific bit is set in the boardflags.
SVN-Revision: 33620
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SVN-Revision: 33619
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SVN-Revision: 33618
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The new version of the ALL0256N now got 8MB SPI NOR flash instead of 4MB.
In order to expose the whole amount of flash, add another image which contains
the corresponding GENERIC_8M mtdparts.
[juhosg: change suffix from '8m' to '8M']
Patch by: Daniel Golle <dgolle@allnet.de>
SVN-Revision: 33614
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Gumstix builds a fake flash image for usage in qemu
SVN-Revision: 33609
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SVN-Revision: 33607
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SVN-Revision: 33606
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SVN-Revision: 33605
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SVN-Revision: 33604
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SVN-Revision: 33603
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SVN-Revision: 33602
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Sometimes the PCIe card indicates that it has a sprom somewhere and we
are able to read the memory region, but it is empty and not valid. In
these cases we should try to use the fallback sprom as a last chance.
SVN-Revision: 33601
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The chip common and the PCIe code are accessing the sprom struct which
is not filled when these cores are initialized. Fix this by adding an
early initialize and fill the sprom struct before accessing it in other
code.
SVN-Revision: 33600
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SVN-Revision: 33599
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SVN-Revision: 33598
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The bcma based SoCs with a ieee80211 core on the SoC and an other
connected via PCIe or USB store the sprom for the SoC with a sb/1/
prefix. The SoC with just one wifi core do not use prefixes. The
BCM4706 do not use a prefix for the SoC part at all, because the prefix
is the path to the ieee80211 core and there is non on the BCM4706.
SVN-Revision: 33597
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