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* mediatek: add support for Bananapi BPi-R3Daniel Golle2022-08-309-2/+920
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Bananapi BPi-R3 is a development router board built around the MediaTek Filogic 830 (MT7986A) SoC. The board can boot either from microSD, SPI-NAND, SPI-NOR or eMMC. Only either SPI-NAND or SPI-NOR can be used at the same time, also only either microSD or eMMC can be used. The various storage options can be selected using small SMD switches on the board. Specs: * MediaTek MT7986A (Filogic 830) 4x ARM Cortex A53 * 4T4R 2.4G 802.11bgnax (MT7975N) * 4T4R 5G 802.11anac/ax (MT7975P) * 2 GB DDR4 RAM * 8 GB eMMC * 128 MB SPI-NAND flash * 32 MB SPI-NOR flash * on-board MT7531 GbE switch * 2x SFP+ (1 GbE / 2.5 GbE) * 5x GbE network port * miniPCIe slot (only USB 2.0 connected) * uSIM slot (connected to miniPCIe interface) * M.2 KEY-E PCIe interface (PCIe x2) * microSD card interface * 26 PIN GPIO Hardware details: https://wiki.banana-pi.org/Banana_Pi_BPI-R3 Working: * all 4 boot methods incl. installation via U-Boot, sysupgrade, ... * copper LAN and WAN ports * SFP1 (connected to gmac1, eth1 in Linux) * WiFi * LEDs * Buttons * PSTORE/ramoops based dual-boot Not Working (missing driver features): * SFP2 (connected to MT7531 switch) Untested: * M.2/NGFF slot (PCIe x2) * mPCIe slot (USB 2.0 + SIM) Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* kernel: add pending mtk_sgmii and phy improvements from @lynxisDaniel Golle2022-08-3010-0/+467
| | | | | | | | | | | | | Add pending patches from Alexander 'lynxis' Couzens which are required for RealTek NBase-T PHYs or SFP+ cages to work when connected to the SGMII interface provided by recent MediaTek SoCs [1]. The patches for MT753x fix link speed limitation on CPU ports observed by many users which is due to reset being carried out wrongly [2]. [1]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669488&state=* [2]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669486&state=* Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* kernel: backport generic phylink validateDaniel Golle2022-08-3056-28/+4446
| | | | | | | Backport generic phylink validate series and make use of it for mtk_eth_soc Ethernet driver as well as mt7530 DSA driver. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* ramips: define Yuncore AX820 switch LEDsThibaut VARÈNE2022-08-292-0/+20
| | | | | | | | | This patch defines the two switch LED to bring them under user control. Fixes: a0e1d3ab7b4f ("ramips: improve YunCore AX820 LEDs") Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org> [rmilecki: leave "label"s in place] Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* realtek: tl-sg2008p: fix labeling of lan portsAlexandru Gagniuc2022-08-291-8/+8
| | | | | | | | The SG2008P has its ethernet ports in the rear, and LEDs in the front. The ports should be labeled lan8->lan1, not lan1->lan8. To resolve this, fix the phy mapping in the "ports" node. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: tl-sg2008p: use correct i2c address for TPS23861Alexandru Gagniuc2022-08-291-2/+2
| | | | | | | | Address 0x30 is a "broadcast" address for the TPS23861. It should not be used by drivers, as all TPS23861 devices on the bus are supposed to respond. Change this to the correct address, 0x28. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: ignore disabled switch portsSander Vanheule2022-08-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | When marking a switch port as disabled in the device tree, by using 'status = "disabled";', the switch driver fails on boot, causing a restart: CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802c3064, ra == 8022b4b4 [ ... ] Call Trace: [<802c3064>] strlen+0x0/0x2c [<8022b4b4>] start_creating.part.0+0x78/0x194 [<8022bd3c>] debugfs_create_dir+0x44/0x1c0 [<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258 [<80397508>] rtl838x_dbgfs_init+0xe0/0x56c This is caused by the DSA subsystem (mostly) ignoring the port, while rtl83xx_mdio_probe() still extracts some details on this disabled port from the device tree, resulting in the usage of a NULL pointer where a port name is expected. By not probing ignoring disabled ports, no attempt is made to create a debugfs directory later. The device then boots as expected without the disabled port. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* ath79: add support for Extreme Networks WS-AP3805iAlbin Hellström2022-08-296-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifications: - SoC: Qualcomm Atheros QCA9557-AT4A - RAM: 2x 128MB Nanya NT5TU64M16HG - FLASH: 64MB - SPANSION FL512SAIFG1 - LAN: Atheros AR8035-A (RGMII GbE with PoE+ IN) - WLAN2: Qualcomm Atheros QCA9557 2x2 2T2R - WLAN5: Qualcomm Atheros QCA9882-BR4A 2x2 2T2R - SERIAL: UART pins at J10 (115200 8n1) Pinout is 3.3V - GND - TX - RX (Arrow Pad is 3.3V) - LEDs: Power (Green/Amber) WiFi 5 (Green) WiFi 2 (Green) - BTN: Reset Installation: 1. Download the OpenWrt initramfs-image. Place it into a TFTP server root directory and rename it to 1D01A8C0.img Configure the TFTP server to listen at 192.168.1.66/24. 2. Connect the TFTP server to the access point. 3. Connect to the serial console of the access point. Attach power and interrupt the boot procedure when prompted. Credentials are admin / new2day 4. Configure U-Boot for booting OpenWrt from ram and flash: $ setenv boot_openwrt 'setenv bootargs; bootm 0xa1280000' $ setenv ramboot_openwrt 'setenv serverip 192.168.1.66; tftpboot 0x89000000 1D01A8C0.img; bootm' $ setenv bootcmd 'run boot_openwrt' $ saveenv 5. Load OpenWrt into memory: $ run ramboot_openwrt 6. Transfer the OpenWrt sysupgrade image to the device. Write the image to flash using sysupgrade: $ sysupgrade -n /path/to/openwrt-sysupgrade.bin Signed-off-by: Albin Hellström <albin.hellstrom@gmail.com> [rename vendor - minor style fixes - update commit message] Signed-off-by: David Bauer <mail@david-bauer.net>
* kernel: enable inside secure driver for MediaTek platformsDaniel Golle2022-08-284-4/+5
| | | | | | | | Older MT7623 ARMv7 SoC as well as new Filogic platforms come with inside-secure,safexcel-eip97 units. Enable them in DTS and select the driver kernel module by default on those platforms. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* mediatek: add filogic subtargetFelix Fietkau2022-08-286-1/+552
| | | | | | | | Initially this covers MT7986 only, but it will later be expanded to cover other Filogic branded platforms by MediaTek Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* mediatek: add mt7986 soc support to the targetSam Shih2022-08-2825-0/+4286
| | | | | | | | | It will be supported by the new filogic subtarget Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* mediatek: mt7622: use variable sector size for spi-norDaniel Golle2022-08-281-0/+1
| | | | | | Make use of minor sector size (4k) on supported SPI-NOR flash chips. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* kernel: replace downstream get_mtd_device_by_node() implementationRafał Miłecki2022-08-284-152/+2
| | | | | | | | | | | | | | Use upstream of_get_mtd_device_by_node() which should behave pretty much the same. Implementation differences: get_mtd_device_by_node() of_get_mtd_device_by_node() ---- ---- np->dev.of_node mtd_get_of_node(np) -EPROBE_DEFER -ENODEV Cc: Bernhard Frauendienst <openwrt@nospam.obeliks.de> Cc: Bernhard Frauendienst <kernel@nospam.obeliks.de> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* realtek: switch RTL838X/RTL839X DT to new clock driverMarkus Stockhausen2022-08-282-20/+141
| | | | | | | | | | | | | | Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work we need to change some nodes: - define the external oscillator speed (25MHz) - define SRAM - add clock controller - Add second CPU for RTL839X - map all devices to new clocks - Remove dummy LXB clock - add CPU OPP table Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: activate clock driver for RTL838X/RTL839X targetsMarkus Stockhausen2022-08-282-0/+40
| | | | | | | | Make use the new clock driver for RTL838X and RTL839x target devices. Of course we will enable their primary consumer (cpufreq-dt) too. To be careful just set the default governor to userspace. As we rely on SRAM activate that module too. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: enable basic config for cpufreq frameworkMarkus Stockhausen2022-08-281-1/+5
| | | | | | | | | | | | | | | | A new clock driver makes more sense if it can be used from consumers like cpufreq. Before we enable the driver we must tell the config that the RTL838X and RTL839X targets allow CPU frequency changing. Even though these targets currently rely on the CPU's internal R4K timer, MIPS_EXTERNAL_TIMER is selected to allow for CPU frequency change testing. The Realtek timers, which are clocked by the Lexra bus, still need to be supported and used in order to provide correct wall times when reclocking the CPU. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [add paragraph about MIPS_EXTERNAL_TIMER to commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add patch to enable new clock driver in kernelMarkus Stockhausen2022-08-281-0/+26
| | | | | | Allow building the clock driver with kernel config options. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: add RTL83XX clock driverMarkus Stockhausen2022-08-286-0/+1151
| | | | | | | | | | | | | | | | | | | Add a new self-contained combined clock & platform driver that allows to access the PLL hardware clocks of RTL83XX devices. Currently it provides info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and additionally allows to change the CPU clocks. Changing the clocks multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and is multithreading safe on the RTL839X. Even a cpufreq initiated change of the CPU clock works fine. Loading the driver will add some meaningful logging. [0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz [0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz, MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [remove trailing whitespaces, C-style SPDX comments for ASM and headers] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add PLL DT binding includesMarkus Stockhausen2022-08-281-0/+15
| | | | | | Add some constants for sharing between DT and drivers. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* kernel: add quirk for Huawei-compatible OEM SFP GE-TDaniel Golle2022-08-261-0/+47
| | | | | | | Ignore TX_FAULT signal on certain cheap copper/TP gigabit Ethernet SFP modules. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* bcm53xx: 5.15: add missing LEDS_BCM63138 config symbolPetr Štetiar2022-08-251-0/+1
| | | | | | | | | Fixes following build issue found during build testing with 5.15.63 kernel: LED Support for Broadcom BCM63138 SoC (LEDS_BCM63138) [N/m/y/?] (NEW) Signed-off-by: Petr Štetiar <ynezz@true.cz>
* kernel: bump 5.15 to 5.15.63John Audia2022-08-2514-28/+28
| | | | | | | | | | All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200 Run-tested: bcm2711/RPi4B, mt7622/RT3200 Signed-off-by: John Audia <therealgraysky@proton.me>
* kernel: bump 5.10 to 5.10.138John Audia2022-08-255-8/+8
| | | | | | All patches automatically rebased. Signed-off-by: John Audia <therealgraysky@proton.me>
* kernel: bump 5.15 to 5.15.62Petr Štetiar2022-08-2392-1488/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deleted following upstreamed patches: bcm27xx: 950-0006-drm-vc4-hdmi-Fix-HPD-GPIO-detection.patch bcm27xx: 950-0420-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx: 950-0425-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx: 950-0432-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx: 950-0433-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx: 950-0435-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx: 950-0436-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx: 950-0437-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx: 950-0438-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx: 950-0443-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx: 950-0445-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch bcm27xx: 950-0475-drm-vc4-Reset-HDMI-MISC_CONTROL-register.patch bcm27xx: 950-0476-drm-vc4-Release-workaround-buffer-and-DMA-in-error-p.patch bcm27xx: 950-0477-drm-vc4-Correct-DSI-divider-calculations.patch bcm27xx: 950-0664-drm-vc4-dsi-Correct-max-divider-to-255-not-7.patch bcm53xx: 072-next-ARM_dts_BCM53015-add-mr26.patch mediatek: 920-linux-next-dts-mt7622-bpi-r64-fix-wps-button.patch Manually rebased following patches: bcm27xx: 950-0004-drm-vc4-hdmi-Remove-the-DDC-probing-for-status-detec.patch bcm27xx: 950-0700-net-phy-lan87xx-Decrease-phy-polling-rate.patch bcm27xx: 950-0711-drm-vc4-Rename-bridge-to-out_bridge.patch bcm27xx: 950-0713-drm-vc4-Remove-splitting-the-bridge-chain-from-the-d.patch bcm27xx: 950-0715-drm-vc4-Convert-vc4_dsi-to-using-a-bridge-instead-of.patch bcm27xx: 950-0787-vc4-drm-vc4_plane-Keep-fractional-source-coords-insi.patch bcm27xx: 950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch Runtime tested on turris-omnia and glinet-b1300. Tested-by: John Audia <therealgraysky@proton.me> [bcm2711/RPi4B, mt7622/RT3200] Signed-off-by: Petr Štetiar <ynezz@true.cz>
* kernel: bump 5.10 to 5.10.137Petr Štetiar2022-08-2322-278/+36
| | | | | | | | | | Removed following upstreamed patch: * bcm53xx: 081-next-ARM_dts_BCM53015-add-mr26.patch All other patches automagically rebased. Signed-off-by: Petr Štetiar <ynezz@true.cz>
* ipq806x: add missing scaling_available_frequencies for dedicated cpufreqChristian Marangi2022-08-212-2/+14
| | | | | | | | | | Add missing scaling_available_frequencies sysfs entry for dedicated cpufreq driver. This sysfs entry is not standard and each cpufreq driver needs to provide it and declare it in the cpufreq driver struct attr. Fixes: 5dbbefcbccc0 ("ipq806x: introduce dedicated krait cpufreq") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ath79: add support for ZyXEL NWA1100-NHSebastian Schaper2022-08-214-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifications: * AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz * 1x Gigabit Ethernet (AR8035), 802.3af PoE Installation: * OEM Web UI is at 192.168.1.2 login as `admin` with password `1234` * Flash factory-AASI.bin The string `AASI` needs to be present within the file name of the uploaded image to be accepted by the OEM Web-based updater, the factory image is named accordingly to save the user from the hassle of manual renaming. TFTP Recovery: * Open the case, connect to TTL UART port (this is the official method described by Zyxel, the reset button is useless during power-on) * Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage` and `mi124_f1e-jffs2` via tftp at 192.168.1.10 * Interrupt uboot countdown, execute commands `run lk` `run lf` to flash the kernel / filesystem accordingly MAC addresses as verified by OEM firmware: use address source LAN *:cc mib0 0x30 ('eth0mac'), art 0x1002 (label) 2g *:cd mib0 0x4b ('wifi0mac') Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
* ath79: add support for ZyXEL NWA1123-ACSebastian Schaper2022-08-214-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifications: * AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz * QCA9882 PCIe card, 802.11ac 2T2R * 1x Gigabit Ethernet (AR8035), 802.3af PoE Installation: * OEM Web UI is at 192.168.1.2 login as `admin` with password `1234` * Flash factory-AAOX.bin The string `AAOX` needs to be present within the file name of the uploaded image to be accepted by the OEM Web-based updater, the factory image is named accordingly to save the user from the hassle of manual renaming. TFTP Recovery: * Open the case, connect to TTL UART port (this is the official method described by Zyxel, the reset button is useless during power-on) * Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage` and `mi124_f1e-jffs2` via tftp at 192.168.1.10 * Interrupt uboot countdown, execute commands `run lk` `run lf` to flash the kernel / filesystem accordingly MAC addresses as verified by OEM firmware: use address source LAN *:1c mib0 0x30 ('eth0mac'), art 0x1002 (label) 2g *:1c mib0 0x4b ('wifi0mac') 5g *:1e mib0 0x66 ('wifi1mac') Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
* ath79: add support for ZyXEL NWA1123-NISebastian Schaper2022-08-214-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifications: * AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz * AR9382 PCIe card, 802.11n 2T2R, 5 GHz * 1x Gigabit Ethernet (AR8035), 802.3af PoE Installation: * OEM Web UI is at 192.168.1.2 login as `admin` with password `1234` * Flash factory-AAEO.bin The string `AAEO` needs to be present within the file name of the uploaded image to be accepted by the OEM Web-based updater, the factory image is named accordingly to save the user from the hassle of manual renaming. TFTP Recovery: * Open the case, connect to TTL UART port (this is the official method described by Zyxel, the reset button is useless during power-on) * Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage` and `mi124_f1e-jffs2` via tftp at 192.168.1.10 * Interrupt uboot countdown, execute commands `run lk` `run lf` to flash the kernel / filesystem accordingly MAC addresses as verified by OEM firmware: use address source LAN *:fb mib0 0x30 ('eth0mac'), art 0x1002 (label) 2g *:fc mib0 0x4b ('wifi0mac') 5g *:fd mib0 0x66 ('wifi1mac') Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
* ath79: add support for ZyXEL NWA1121-NISebastian Schaper2022-08-214-2/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifications: * AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz * 1x Gigabit Ethernet (AR8035), 802.3af PoE Installation: * OEM Web UI is at 192.168.1.2 login as `admin` with password `1234` * Flash factory-AABJ.bin The string `AABJ` needs to be present within the file name of the uploaded image to be accepted by the OEM Web-based updater, the factory image is named accordingly to save the user from the hassle of manual renaming. TFTP Recovery: * Open the case, connect to TTL UART port (this is the official method described by Zyxel, the reset button is useless during power-on) * Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage` and `mi124_f1e-jffs2` via tftp at 192.168.1.10 * Interrupt uboot countdown, execute commands `run lk` `run lf` to flash the kernel / filesystem accordingly MAC addresses as verified by OEM firmware: use address source LAN *:cc mib0 0x30 ('eth0mac'), art 0x1002 (label) 2g *:cd mib0 0x4b ('wifi0mac') Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
* ramips: mt7621-dts: mux phy0/4 to gmac1Arınç ÜNAL2022-08-20113-635/+1429
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mux the MT7530 switch's phy0/4 to the SoC's gmac1 on devices where RGMII2 pins are available. This achieves 2 Gbps total bandwidth to the CPU using the second RGMII. The ports called "wan" are muxed where possible. On a minority of devices, this is not possible. Those cases: mt7621_ampedwireless_ally-r1900k.dts: lan3 mt7621_ubnt_edgerouter-x.dts: eth0 mt7621_gnubee_gb-pc1.dts: ethblue mt7621_linksys_re6500.dts: lan1 mt7621_netgear_wac104.dts: lan4 mt7621_tplink_eap235-wall-v1.dts: lan0 mt7621_tplink_eap615-wall-v1.dts: lan0 mt7621_ubnt_usw-flex.dts: lan1 The "wan" port is just what the vendor designated on the board/plastic chasis of the device. On a technical level, there is no difference between a lan and wan port on MT7621AT, MT7621DAT and MT7621ST SoCs. Prefer connecting to WAN via the port described above for these devices to benefit the feature brought with this patch. mt7621_d-team_newifi-d2.dts cannot benefit this feature, although it looks like it should, because the rgmii2 pins are wired to unused components. Tested on a range of devices documented on the GitHub PR. Link: https://github.com/openwrt/openwrt/pull/10238 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
* ramips: mt7621-dts: remove DTS_LEGACY from ethernet nodeArınç ÜNAL2022-08-201-2/+0
| | | | | | | | | Remove DTS_LEGACY put for claiming pin groups for the ethernet node from the ethernet node. It's not an old kernel trait. These bindings need to be there on the newer kernels as well. Fixes: a3764ee29dd0 ("ramips: add linux 5.15 support for mt7621") Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
* ramips: mt7621-dts: do not claim rgmii2 group as gpio for certain devicesArınç ÜNAL2022-08-2011-46/+23
| | | | | | | | | | | | | | | These devices do not use rgmii2 as gpio, therefore remove rgmii2 pin group from state-default. Remove overwriting the ethernet node for these devices. Move claiming the rgmii2 group from mt7621_zyxel_nwa-ax.dtsi to mt7621_zyxel_nwa50ax.dts as it's only the latter using rgmii2 pins as gpio. Remove duplicate ethernet overwrite from mt7621_tplink_archer-x6-v3.dtsi. Claim rgmii2 group as gpio on mt7621_bolt_arion.dts as it uses an rgmii2 pin, 26, as gpio. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
* ramips: fix GB-PC1 and GB-PC2 device supportArınç ÜNAL2022-08-207-63/+69
| | | | | | | | | | | | | | | | Change switch port labels to ethblack & ethblue. Change lan1 & lan2 LEDs to ethblack_act & ethblue_act and fix GPIO pins. Add the external phy with ethyellow label on the GB-PC2 devicetree. Do not claim rgmii2 as gpio, it's used for ethernet with rgmii2 function. Enable ICPlus PHY driver for IP1001 which GB-PC2 has got. Update interface name and change netdev function. Enable lzma compression to make up for the increased size of the kernel. Make spi flash bindings on par with mainline Linux to fix read errors. Tested on GB-PC2 by Petr. Tested-by: Petr Louda <petr.louda@outlook.cz> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
* realtek: more generic platform initializationMarkus Stockhausen2022-08-201-5/+34
| | | | | | | | | Platform startup still "guesses" the CPU clock speed by DT fixed values. If possible take clock rates from a to be developed driver and align to MIPS generic platfom initialization code. Pack old behaviour into a fallback function. We might get rid of that some day. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: d-link: add support for dgs-1210-10mpDaniel Groth2022-08-202-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General hardware info: ------------------------------------------------------------------------------- D-Link DGS-1210-10MP is a switch with 8 ethernet ports and 2 SFP ports, all ports Gbit capable. It is based on a RTL8380 SoC @ 500MHz, DRAM 128MB and 32MB flash. All ethernet ports are 802.3af/at PoE capable with a total PoE power budget of 130W. File info: ------------------------------------------------------------------------------- The dgs-1210-10mp is very similar to dgs-1210-10p so I used that as a start. rtl838x.mk: - Removed lua-rs232 package since it was a leftover from the old rtl83xx-poe package. - Updated the soc to 8380. - Specified device variant: F. - Installed the new realtek-poe package. rtl8380_d-link_dgs-1210-10mp.dts: - Moved dgs-1210 family common parts and non PoE related ports on rtl8231 to the new device tree dtsi files. Serial connection: ------------------------------------------------------------------------------- The UART for the SoC (115200 8N1) is available close to the front panel next to the LED/key card connector via unpopulated standard 0.1" pin header marked j4. Pin1 is marked with arrow and square. Pin 1: Vcc 3,3V Pin 2: Tx Pin 3: Rx Pin 4: Gnd Installation with TFTP from u-boot ------------------------------------------------------------------------------- I originally used the install procedure: 'OpenWrt installation using the TFTP method and serial console access' found in the device wiki for the dgs-1210-16. < https://openwrt.org/toh/d-link/dgs-1210-16_g1#openwrt_installation_using _the_tftp_method_and_serial_console_access > About the realtek-poe package ------------------------------------------------------------------------------- The realtek-poe package is installed but there isn't any automatic PoE config setting at this time so for now the PoE config must be edited manually. Original OEM hardware/firmware data at first installation ------------------------------------------------------------------------------- It has been installed, developed, and tested on a device with these OEM hardware and firmware versions. - U-boot: 2011.12.(2.1.5.67086)-Candidate1 (Jun 22 2020 - 15:03:58) - Boot version: 1.01.001 - Firmware version: 6.20.007 - Hardware version: F1 Things to be done when support are developed ------------------------------------------------------------------------------- - realtek-poe has been included in OpenWrt but the automatic config handling has not been solved yet so in the future there will probably be some minor updates for this device to handle the poe config. - LED link_act and poe are per function supposed to be connected to the PoE system. But some software development is also needed to make this LED work and shift the LED array between act and poe indication and to shift the mode lights with mode key. - LED poe_max should probably be used as straight forward error output from the realtek-poe package error handling. But no code has been written for this. - SFP is currently not hot pluggable. Development is under progress to get working I2C communication with SFP and have them hot pluggable. When any device in the dgs-1210 family gets this working, I expect it should be possible to implement the same solution in this device. Signed-off-by: Daniel Groth <flygarn12@gmail.com> [Capitalisation of abbreviations, DEVICE_VARIANT and update filenames, device compatibles on single line] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: d-link: dgs-1210 remake of the device treeDaniel Groth2022-08-206-133/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I have collected the known information from the dts files we have. After that I made a new device tree that should work for this whole D-Link switch family. This device tree is based on modules where you first select which SoC group the device belongs to. Then you include the GPIO dtsi file depending on what hardware your device has, see examples below. This tree is also expandable for more hardware, see the part 'Future expansion possibilities' further down. ------------------------------------------------------------------------------- The device tree now looks like this: ---------------- | rtl838x.dtsi | // Note 1. ---------------- | | --------------------------------------- | rtl838x_d-link_dgs-1210_common.dtsi | // Note 2. --------------------------------------- | | -------------- |-------| device.dts | // Note 3. | -------------- | ------------------------------------- | rtl83xx_d-link_dgs-1210_gpio.dtsi | // Note 4. ------------------------------------- | | -------------- |-------| device.dts | // Note 5. -------------- Note 1; Included in rtl838x_d-link_dgs-1210_common.dtsi. Note 2; SoC level information and memory mapping. Choose which one to include in the device dts. Note 3; At this point dgs-1210-16 will come out here. Note 4; In this dtsi only common board hardware based on the rtl8231 is found. No PoE based hardware in this dtsi. In this dtsi there is no <#include> to above *_common.dtsi. Note 5; Device dts with only rtl8231 based hardware without PoE will come out here. ------------------------------------------------------------------------------- How to set up in dts file: The device dts will have one of these two <#include> alternatives. This alternative includes only common features: <#include "rtl838x_d-link_dgs-1210_common.dtsi"> This alternative includes common and the rtl8231 GPIO (no PoE) features: <#include "rtl838x_d-link_dgs-1210_common.dtsi"> <#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"> ------------------------------------------------------------------------------- Implementation: Finally, I also implemented this new family device tree on the current supported devices: dgs-1210-10p dgs-1210-16 dgs-1210-20 dgs-1210-28 The implementation for the dgs-1210-10p is different. I have removed the information from the rtl8382_d-link_dgs-1210-10p.dts that is already present in rtl838x_d-link_dgs-1210_common.dtsi. Since the rest isn't officially probed in the device dts I do not want to include the rtl83xx_d-link_dgs-1210_gpio.dtsi with dgs-1210-10p.dts. Since I don't have these devices to test on I have built the original firmware for each one of these devices before this change and saved the dtb file and then compared the original dtb file with the dtb file built with this new device tree. ------------------------------------------------------------------------------- Future expansion possibilities: In parallel with the rtl838x_d-link_dgs-1210_common.dtsi in the tree map we can make a rtl839x_d-link_dgs-1210_common.dtsi to use the rtl839x.dtsi if the need arises with more devices based on rtl839x soc. When we have more PoE devices so the hardware map for these gets more clear we can make a rtl83xx_d-link_dgs-1210_poe.dtsi below the rtl83xx_d-link_dgs-1210_gpio.dtsi in the tree map. I looked at the port and switch setup to see if it could be moved to the dtsi. I decided not to touch this part now. The reason was that there isn't really any meaningful way this could be shared between the devices. The only thing in common over the family is the 8+2sfp ports on the dgs-1210-10xx device. And then there is the hot plug SFP and I2C ports that aren’t implemented on any device. So maybe when we see the whole port map for the family then maybe the ports can be moved to a *_common.dtsi but I don't think it is the right moment for that now. Signed-off-by: Daniel Groth <flygarn12@gmail.com> [Capitalisation of abbreviations and 'D-Link'] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* ramips: get MAC addr from the encrypted partition (WG4хх223)Mikhail Zhilkin2022-08-193-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit resolves #10062. Adds decryption of the Arcadyan WG4xx223 configuration partition (board_data)to get base MAC address from it. As a result, after this change the hack with saving MAC addressees to u-boot-env before installation of OpenWrt is no longer necessary. This is necessary for the following devices: - Beeline Smartbox Flash (Arcadyan WG443223) - MTS WG430223 (Arcadyan WG430223) Example: +----------------+-------------------+------------------------+ | | MTS WG430223 | Beeline Smartbox Flash | +----------------+-------------------+------------------------+ | base mac (mtd) | A4:xx:xx:51:xx:F4 | 30:xx:xx:51:xx:06 | | label | A4:xx:xx:51:xx:F4 | 30:xx:xx:51:xx:09 | | LAN | A4:xx:xx:51:xx:F6 | 30:xx:xx:51:xx:09 | | WAN | A4:xx:xx:51:xx:F4 | 30:xx:xx:51:xx:06 | | WLAN_2g | A4:xx:xx:51:xx:F5 | 30:xx:xx:51:xx:07 | | WLAN_5g | A6:xx:xx:21:xx:F5 | 32:xx:xx:41:xx:07 | +----------------+-------------------+------------------------+ Collected statistic shows that the 2-4th bits of the 7th byte of the WLAN_5g MAC are the constant (see #10062 for more details): - Beeline Smartbox Flash - 100 - MTS WG430223 - 010 Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
* ramips: fix ZyXEL NWA55AXE model nameDavid Bauer2022-08-181-1/+1
| | | | | | The model name was missing a letter. Signed-off-by: David Bauer <mail@david-bauer.net>
* bcm4908: enable NVMEM U-Boot env data driverRafał Miłecki2022-08-171-0/+3
| | | | | | It's needed for devices with U-Boot bootloader. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* kernel: add CONFIG_NVMEM_U_BOOT_ENV symbol to configsRafał Miłecki2022-08-172-0/+2
| | | | | | | | This fixes: U-Boot environment variables support (NVMEM_U_BOOT_ENV) [N/m/y/?] (NEW) Fixes: 34cf310435044 ("kernel: backport U-Boot environment data NVMEM driver") Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* kernel: backport U-Boot environment data NVMEM driverRafał Miłecki2022-08-179-14/+714
| | | | | | It parses U-Boot env data into NVMEM cells. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* kernel: rename 5.20 patches to 6.0Rafał Miłecki2022-08-1714-0/+0
| | | | Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* mvebu: leds: Turris Omnia improvementsJosef Schlehofer2022-08-163-0/+182
| | | | | | | It backports this patch series, which is currently on review: https://lore.kernel.org/linux-leds/20220704105955.15474-1-kabel@kernel.org/T/#rb89a4ca5a836f17bdcc53d65549e0b1779bb6a18 Signed-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>
* mvebu: backport pending DTS changes for Turris OmniaJosef Schlehofer2022-08-162-0/+86
| | | | | | | | Backport pending patches: - https://lore.kernel.org/linux-arm-kernel/20220704113622.18887-1-kabel@kernel.org/ - https://lore.kernel.org/linux-arm-kernel/20220704113622.18887-2-kabel@kernel.org/ Signed-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>
* mvebu: refresh the 5.15 kconfigsRui Salvaterra2022-08-163-10/+4
| | | | | | Clean them up. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
* mvebu: add Linux 5.15 as testing kernelRui Salvaterra2022-08-161-0/+1
| | | | | | Run-tested on the cortexa9 subtarget (Turris Omnia). Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
* mvebu: update the kconfigs for 5.15Rui Salvaterra2022-08-163-28/+38
| | | | | | And remove irrelevant stuff while at it. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
* mvebu: copy 5.10 kconfigs to 5.15Rui Salvaterra2022-08-164-0/+610
| | | | | | Will be refreshed/updated later. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
* mvebu: refresh 5.15 patchesRui Salvaterra2022-08-1616-83/+32
| | | | | | | | | | | | | | | | Deleted (upstreamed): 303-linksys_hardcode_nand_ecc_settings.patch [1] Deleted (not needed): 314-arm64-dts-uDPU-switch-PHY-operation-mode-to-2500base.patch [2] Manually rebased: 700-mvneta-tx-queue-workaround.patch [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4daff3e5b42422cd4af758cc7768223d2b7f6e14 [2] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=7f73acade0cde61341cb77e0dc74de51ac059d4f Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
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