aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux
Commit message (Collapse)AuthorAgeFilesLines
* kernel: bump 5.4 to 5.4.126John Audia2021-06-2612-23/+39
| | | | | | | | | Manually rebased: bcm27xx/patches-5.4/950-0089-cgroup-Disable-cgroup-memory-by-default.patch All other patches automatically rebased. Signed-off-by: John Audia <graysky@archlinux.us>
* kernel: bump 5.4 to 5.4.125John Audia2021-06-261-9/+9
| | | | | | | | | | All patches automatically rebased. Build system: x86_64 Build-tested: ipq806x/R7800 Run-tested: ipq806x/R7800 Signed-off-by: John Audia <graysky@archlinux.us>
* kernel: bump 5.10 to 5.10.46Rui Salvaterra2021-06-262-1/+2
| | | | | | | | Add the new symbol to the generic kconfig. No deleted or manually refreshed patches. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
* ramips: ethernet: ralink: rewrite esw_rt3050 to support link statesAlexander Couzens2021-06-253-45/+103
| | | | | | | | Ensure the esw is initialized before the ethernet device is sending packets. Further implement carrier detection similar to mt7620. If any port has a link, the ethernet device will detect a carrier. Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
* ramips: ethernet: ralink: allow to return EPROBE_DEFER on switch_initAlexander Couzens2021-06-251-2/+7
| | | | | | | For rt3050 the switch needs to be initialized before the ethernet start sending packets. Allow switch_init to return -EPROBE_DEFER. Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
* ramips: ethernet: ralink: move reset of the esw into the esw instead of feAlexander Couzens2021-06-254-13/+6
| | | | | | The esw reset should only done by the esw driver and not by the fe itself. Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
* ramips: ethernet: ralink: use the reset controller api for esw & ephyAlexander Couzens2021-06-255-15/+45
| | | | | | Instead of writing direct into the reset registers. Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
* ramips: ethernet: ralink: add fe_reset_fe() to reset fe via reset controllerAlexander Couzens2021-06-255-25/+23
| | | | | | | | The dts defines the reset fe for all architectures. However the soc code used direct register access of the reset controller. Replace the custom soc reset with a generic fe_reset_fe(). Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
* ramips: ethernet: ralink: add struct fe_priv as context to fe_reset()Alexander Couzens2021-06-256-7/+7
| | | | | | | | The fe_reset function direct access the reset controller instead using the reset controller api. In preparation to use the reset controller. Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
* ipq40xx: specify FritzBox 7530 LAN port label numbersRafał Miłecki2021-06-241-1/+1
| | | | | | | | | This helps managing LAN ports. Ref: https://forum.openwrt.org/t/openwrt-21-02-0-second-release-candidate/98026/121 Fixes: 95b0c07a618f ("ipq40xx: add support for FritzBox 7530") Cc: David Bauer <mail@david-bauer.net> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* ramips: fix software reboot failure on HILINK HLK-7628NLiu Yu2021-06-231-0/+1
| | | | | | | | | | | In the new kernel version 5.X,reboot will fail. When SOC is reset, flash has not exited the 4-byte address mode, which causes the operation mode mismatch of flash during boot.Add broken-flash-reset to make flash exit 4-byte address mode before SOC reset Signed-off-by: Liu Yu <f78fk@live.com>
* ramips: add missing "pinctrl-names" for Youku YK1Shiji Yang2021-06-231-0/+1
| | | | | | | | | Without this definition ethernet led can work as usual, but it's better to re-add it. Relying on default values may cause uncontrollable factors. Fixes: 882a6116d3d6 ("ramips: improve pinctrl for Youku YK-L1") Signed-off-by: Shiji Yang <yangshiji66@qq.com>
* ramips: mt7620: disable SOC VLANs for external switchesMichael Pratt2021-06-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | These boards have AR8327 or QCA8337 external ethernet switch. The SOC also has it's own internal switch where VLAN is now enabled by default. Changes to preinit caused all switches to have VLANs enabled by default even if they are not configured with a topology in uci_defaults (see commit f017f617aecbd47debd4d3a734dc0e471342db96) When both internal and external switches have VLANs, and the external switch has both LAN and WAN, the TX traffic from the SOC cannot flow to the tagged port on the external switch because the VLAN IDs are not matching. So disable the internal switch VLANs by default on these boards. Also, add a topology for the internal switch, so that on LuCI there is not an "unknown topology" warning. In theory, it may be possible to have LAN ports on both switches through internal and external PHYs, but there are no known boards that have this. Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: ethernet: use more macros and bump versionMichael Pratt2021-06-234-7/+11
| | | | | | | | | | | | | | | Define and use some missing macros, and use them instead of BIT() or numbers for more readable code. Add comment for a bit change that seems unrelated to ethernet but is actually needed (PCIe Root Complex mode). Remove unknown and unused macro RST_CTRL_MCM (probably from MT7621 / MT7622) This is the last of a series of fixes, so bump version. Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: fix RGMII TXID PHY modeMichael Pratt2021-06-231-1/+1
| | | | | | | | | | | | | | the register bits for TX delay and RX delay are opposites: when TX delay bit is set, delay is enabled when RX delay bit is set, delay is disabled So, when both bits are unset, it is RX delay and when both bits are set, it is TX delay Note: TXID is the default RGMII mode of the SOC Fixes: 5410a8e2959a ("ramips: mt7620: add rgmii delays support") Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: add ephy-disable option to switch driverMichael Pratt2021-06-232-2/+13
| | | | | | | | | | | | | | Add back the register write to disable internal PHYs as a separate option in the code that can be set using a DTS property. Set the option to true by default when an external mt7530 switch is identified. This makes the driver more in sync with original SDK code while keeping the lines separated into different options to accommodate any board with any PHY layout. Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: move mt7620_mdio_mode() to ethernet driverMichael Pratt2021-06-235-74/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The function mt7620_mdio_mode is only called once and both the function and mdio_mode block have been named incorrectly, leading to confusion and useless commits. These lines in the mdio_mode block of mt7620_hw_init are only intended for boards with an external mt7530 switch. (see commit 194ca6127ee18cd3a95da4d03f02e43b5428c0bb) Therefore, move lines from mdio_mode to the place in soc_mt7620.c where the type of mt7530 switch is identified, and move lines from mt7620_mdio_mode to a main function. mt7620_mdio_mode was called from mt7620_gsw_init where the priv struct is available, so the lines must stay in mt7620_gsw_init function. In order to keep things as simple as possible, keep the DTS property related function calls together, by moving them from mt7620_gsw_probe to init. Remove the now useless DTS properties and extra phy nodes. Fixes: 5a6229a93df8 ("ramips: remove superfluous & confusing DT binding") Fixes: b85fe43ec8c4 ("ramips: mt7620: add force use of mdio-mode") Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: use DTS to set PHY base address for external PHYsMichael Pratt2021-06-2324-7/+60
| | | | | | | | | | | | | | | | | | | | | | | Set the PHY base address to 12 for mt7530 and 8 for others, which is based on the default setting for some devices from printing the register with the following command after it is written to by uboot during the boot cycle. `md 0x10117014 1` PHY_BASE option only uses 5 bits of the register, bits 16 to 20, so use 8-bit integer type. Set the option using the DTS property mediatek,ephy-base and create the gsw node if missing. Also, added a kernel message to display the EPHY base address. Note: If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf) then there is adverse effects with Atheros switches. Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: allow both internal and external PHYsMichael Pratt2021-06-231-62/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the new variable ephy_base was introduced, it was not applied to the if block for mdio_mode. The first line in the mdio_mode if block sets the EPHY base address to 12 in the SOC by writing a register, but the corresponding variable in the driver was still set to the default of 0. This causes subsequent lines that write registers with the function _mt7620_mii_write to write to PHY addresses 0 through 4 while internal PHYs have been moved to addresses 12 through 16. All of these lines are intended only for PHYs on the SOC internal switch, however, they are being written to external ethernet switches if they exist at those PHY addresses 0 through 4. This causes some ethernet ports to be broken on boards with AR8327 or QCA8337 switch. Other suggested fixes move those lines to the else block of mdio_mode, but removing the else block completely also fixes it. Therefore, move the lines to the mt7620_hw_init function main block, and have only one instance of the function mtk_switch_w32 for writing the register with the EPHY base address. In theory, this also allows for boards that have both external switches and internal PHYs that lead to ethernet ports to be supported. Fixes: 391df3782914 ("ramips: mt7620: add EPHY base mdio address changing possibility") Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: fix ethernet driver GMAC port initMichael Pratt2021-06-232-15/+9
| | | | | | | | | | | | | | | | | | | | | | | A workaround was added to the switch driver to set SOC port 4 as an RGMII GMAC interface based on the DTS property mediatek,port4-gmac. (previously mediatek,port4) However, the ethernet driver already does this, but is being blocked by a return statement whenever the phy-handle and fixed-link properties are both missing from nodes that define the port properties. Revert the workaround, so that both the switch driver and ethernet driver are not doing the same thing and move the phy-handle related lines down so nothing is ending the function prematurely. While at it, clean up kernel messages and delete useless return statements. Fixes: f6d81e2fa1f1 ("mt7620: gsw: make IntPHY and ExtPHY share mdio addr 4 possible") Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: remove useless GMAC nodesMichael Pratt2021-06-234-27/+4
| | | | | | | | | | | | | | | | | | | These nodes are used for configuring a GMAC interface and for defining external PHYs to be accessed with MDIO. None of this is possible on MT7620N, only MT7620A, so remove them from all MT7620N DTS. When the mdio-bus node is missing, the driver returns -NODEV which causes the internal switch to not initialize. Replace that return so that everything works without the DTS node. Also, an extra kernel message to indicate for all error conditions that mdio-bus is disabled. Fixes: d482356322c9 ("ramips: mt7620n: add mdio node and disable port4 by default") Fixes: aa5014dd1a58 ("ramips: mt7620n: enable port 4 as EPHY by default") Signed-off-by: Michael Pratt <mcpratt@pm.me>
* ramips: mt7620: simplify DTS properties for GMACMichael Pratt2021-06-2341-125/+23
| | | | | | | | | | | | | | | | | | | There are only 2 options in the driver for the function of mt7620 internal switch port 4: EPHY mode (RJ-45, internal PHY) GMAC mode (RGMII, external PHY) Let the DTS property be boolean instead of string where EPHY mode is the default. Fix how the properties are written for all DTS that use them, and add missing nodes where applicable, and remove useless nodes, and minor DTS formatting. Signed-off-by: Michael Pratt <mcpratt@pm.me>
* realtek: Fix failsafe modeHauke Mehrtens2021-06-222-0/+19
| | | | | | | | | | | | | | | The RTL8380-RTL9300 switches only forward packets when VLAN ID 1 is configured. Do not use the standard failsafe configuration for DSA accessing the default port directly, but configure a switch on the lan1 interface instead. This will add the VLAN ID 1 configuration to the switch: $ bridge vlan show port vlan-id lan1 1 PVID Egress Untagged switch 1 PVID Egress Untagged Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* kernel: Backport patch to automatically bring up DSA master when opening ↵Hauke Mehrtens2021-06-2221-40/+210
| | | | | | | | | | | | user port Without this patch we have to manually bring up the CPU interface in failsafe mode. This was backported from kernel 5.12. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Rafał Miłecki <rafal@milecki.pl>
* kernel-5.4: backport latest patches for wireguardJason A. Donenfeld2021-06-2212-0/+1514
| | | | | | | | | | These are the latest patches that just landed upstream for 5.13, will be backported by Greg into 5.10 (because of stable@), and are now in the 5.4 backport branch of wireguard: https://git.zx2c4.com/wireguard-linux/log/?h=backport-5.4.y Cc: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Tested-by: Stijn Segers <foss@volatilesystems.org>
* kernel: bump 5.10 to 5.10.44Rui Salvaterra2021-06-222-1/+2
| | | | | | | | Add the new symbol to the generic kconfig. No deleted or manually refreshed patches. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
* realtek: Fix buffer length calculation on RTL8380 with CRC offloadBirger Koblitz2021-06-221-9/+7
| | | | | | | | | | | | | Fixes the buffer and packet length calculations for Ethernet TX on the RTL8380 SoC when CRC calculation offload is enabled. CRC-offload is always done by the SoC, but additional CRC calculation was previously done also by the kernel. It also fixes detection of the DSA tag for packets on RTL8390 SoCs for ports > 28. v2 has correct whitespace Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
* bcm4908: fix Ethernet broken state after interface restartRafał Miłecki2021-06-221-0/+43
| | | | | | This fixes traffic stalls after ifdown & ifup. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* ath79: add missing GPIO_LATCH symbolDavid Bauer2021-06-222-0/+2
| | | | | | Fixes commit 7b8931678c36 ("ath79: add gpio-latch driver for MikroTik RouterBOARDs") Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: ar934x: fix mounting issues if subpage is not supportedKoen Vandeputte2021-06-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the option to disable subpage writing is only set when a HW ECC engine is used. Some boards lack a HW ECC engine and use software for that. In this case, this NAND option does not get set when the NAND chip does not support it, resulting in mounting errors. Move the setting of this option to a generic init location so it gets set for all types where required. While at it, also OR the option instead of just setting it so we don't overwrite potential flags being set somewhere else. Before: [ 1.681273] UBI: auto-attach mtd2 [ 1.684669] ubi0: attaching mtd2 [ 1.688877] ubi0 error: validate_ec_hdr: bad VID header offset 2048, expected 512 [ 1.696469] ubi0 error: validate_ec_hdr: bad EC header [ 1.701712] Erase counter header dump: [ 1.705512] magic 0x55424923 [ 1.709322] version 1 [ 1.712330] ec 1 [ 1.715331] vid_hdr_offset 2048 [ 1.718610] data_offset 4096 [ 1.721880] image_seq 1462320675 [ 1.725680] hdr_crc 0x12255a15 After: 1.680917] UBI: auto-attach mtd2 [ 1.684308] ubi0: attaching mtd2 [ 2.954504] random: crng init done [ 3.142813] ubi0: scanning is finished [ 3.163455] ubi0: attached mtd2 (name "ubi", size 124 MiB) [ 3.169069] ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes [ 3.176037] ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048 [ 3.182942] ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096 [ 3.190013] ubi0: good PEBs: 992, bad PEBs: 0, corrupted PEBs: 0 [ 3.196102] ubi0: user volume: 3, internal volumes: 1, max. volumes count: 128 [ 3.203434] ubi0: max/mean erase counter: 2/0, WL threshold: 4096, image sequence number: 1462320675 [ 3.212700] ubi0: available PEBs: 0, total reserved PEBs: 992, PEBs reserved for bad PEB handling: 20 [ 3.222124] ubi0: background thread "ubi_bgt0d" started, PID 317 [ 3.230246] block ubiblock0_1: created from ubi0:1(rootfs) [ 3.235819] ubiblock: device ubiblock0_1 (rootfs) set to be root filesystem [ 3.256830] VFS: Mounted root (squashfs filesystem) readonly on device 254:0. Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* ath79: add support for MikroTik RouterBOARD 912UAG-2HPnDDenis Kalashnikov2021-06-215-0/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has been supported in the ar71xx. Links: * https://mikrotik.com/product/RB912UAG-2HPnD * https://openwrt.org/toh/hwdata/mikrotik/mikrotik_rb912uag-2hpnd This also supports the 5GHz flavour of the board. Hardware: * SoC: Atheros AR9342, * RAM: DDR 64MB, * SPI NOR: 64KB, * NAND: 128MB, * Ethernet: x1 10/100/1000 port with passive POE in, * Wi-Fi: 802.11 b/g/n, * PCIe, * USB: 2.0 EHCI controller, connected to mPCIe slot and a Type-A port -- both can be used for LTE modem, but only one can be used at any time. * LEDs: 5 general purpose LEDs (led1..led5), power LED, user LED, Ethernet phy LED, * Button, * Beeper. Not working: * Button: it shares gpio line 15 with NAND ALE and NAND IO7, and current drivers doesn't easily support this configuration, * Beeper: it is connected to bit 5 of a serial shift register (tested with sysfs led trigger timer). But kmod-gpio-beeper doesn't work -- we left this as is for now. Flashing: * Use the RouterBOARD Reset button to enable TFTP netboot, boot kernel and initramfs and then perform sysupgrade. * From ar71xx OpenWrt firmware run: $ sysupgrade -F /tmp/<sysupgrade.bin> For more info see: https://openwrt.org/toh/mikrotik/common. Co-Developed-by: Koen Vandeputte <koen.vandeputte@citymesh.com> Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
* ath79: add NAND driver for MikroTik RB91xG seriesDenis Kalashnikov2021-06-214-0/+420
| | | | | | | | | | | | | Main part is copied from ar71xx original driver rb91x_nand written by Gabor Juhos <juhosg@openwrt.org>. What is done: * Support of kernel 5.4 and 5.10, * DTS support, * New gpio API (gpiod_*) support. Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
* ath79: add gpio-latch driver for MikroTik RouterBOARDsDenis Kalashnikov2021-06-213-0/+252
| | | | | | | | | | | | This is a slighty modified version of ar71xx gpio-latch driver written by Gabor Juhos <juhosg@openwrt.org>. Changes: * DTS support, * New gpio API (gpiod_*). Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
* bcm4908: add kmod-gpio-button-hotplugRafał Miłecki2021-06-211-0/+1
| | | | | | | | All bcm4908 devices are expected to have GPIO buttons to make relevant package selected by default. This "fixes" triggering failsafe mode. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* ramips: clean up dlink_dir-8xx-r1 recipeAdrian Schmutzler2021-06-201-5/+5
| | | | | | | | * only add factory.bin when it's defined * fix check-size vs. append-metadata * whitespace/line break cleanup Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ramips: reorganize DTSI files for D-Link DIR-8xxAdrian Schmutzler2021-06-208-27/+40
| | | | | | | | | | | * Remove micro-DTSI mt7621_dlink_dir-882-x1.dtsi to ease reading config without too much inheritance * Use "separate" partitioning DTSIs so we can use the partitioning without a complete match on the other settings (i.e. without the former parent DTSI) * Rename files to express the new organization Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* kernel: disable CONFIG_PCIE_BUS_PERFORMANCEFelix Fietkau2021-06-181-2/+2
| | | | | | | | | The option was added in 5.9 and for some reason, it is causing performance issues at least on an APU2 board with the igb device. Switch CONFIG_PCIE_BUS_DEFAULT to fix the performance issues and match the older kernel's behavior Signed-off-by: Felix Fietkau <nbd@nbd.name>
* kernel: make cryptoapi support needed by mac80211 built-inFelix Fietkau2021-06-181-9/+16
| | | | | | | This reduces the flash space impact, since built-in code is much smaller than a bunch of kernel modules on squashfs Signed-off-by: Felix Fietkau <nbd@nbd.name>
* kernel: bump 5.10 to 5.10.43Rui Salvaterra2021-06-147-16/+16
| | | | | | No deleted or manually refreshed patches. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
* ramips: refresh at803x patchDavid Bauer2021-06-141-1/+1
| | | | | | | | This patch failed to apply, breaking builds for the ramips target. Fixes commit c44cefceb3ad ("generic: kernel 5.4: fix probe error for AR803x PHYs") Signed-off-by: David Bauer <mail@david-bauer.net>
* kernel: move some drm symbols to generic configTomasz Maciej Nowak2021-06-137-6/+3
| | | | | | These are architecture independent, so move them to generic config. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
* tegra: add support for kernel 5.10Tomasz Maciej Nowak2021-06-133-8/+24
| | | | | | Mark it as testing for now. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
* tegra: copy files for kernel 5.10Tomasz Maciej Nowak2021-06-133-0/+602
| | | | | | Dumb copy of current kernel 5.4 config and patches. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
* tegra: refresh kernel configTomasz Maciej Nowak2021-06-131-88/+2
| | | | | | | Recent filtering rules alow to trim the kernel configuration in size, do that to reduce the diff between current config and upcoming one. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
* ath79: add support for TP-Link TL-WR841HP v3Andy Lee2021-06-134-2/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifications: - QCA9533 SoC, 8 MB nor flash, 64 MB DDR2 RAM - 2x2 9dBi antenna, wifi 2.4Ghz 300Mbps - 4x Ethernet LAN 10/100, 1x Ethernet WAN 10/100 - 1x WAN, LAN, Wifi, PWR, WPS, RE Leds - Reset, Wifi on/off, WPS, RE buttons - Serial UART at J4 onboard: 3.3v GND RX TX, 1152008N1 Label MAC addresses based on vendor firmware: LAN *:ea label WAN *:eb label +1 2.4 GHz *:ea label The label MAC address in found in u-boot 0x1fc00 Installation: Upload openwrt-ath79-generic-tplink_tl-wr841hp-v3-squashfs-factory.bin from stock firmware webgui. Maybe we need rename to shorten file name due to stock webgui error. Revert back to stock firmware instructions: - set your PC to static IP address 192.168.0.66 netmask 255.255.255.0 - download stock firmware from Tp-link website - put it in the root directory of tftp server software - rename it to wr841hpv3_tp_recovery.bin - power on while pressing Reset button until any Led is lighting up - wait for the router to reboot. done Forum support topic: https://forum.openwrt.org/t/support-for-tp-link-tl-wr841hp-v3-router Signed-off-by: Andy Lee <congquynh284@yahoo.com> [rebase and squash] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* apm821xx: move CONFIG_REGULATOR to target configDavid Bauer2021-06-133-1/+2
| | | | | | | | | | | | This moves CONFIG_REGULATOR to the target config instead of the subtarget config. For kernel 5.10, CONFIG_AT803X_PHY depends on CONFIG_REGULATOR. As we do not have a size constraint, move this symbol to the target configuration for kernel 5.4 as well as 5.10. Reported-by: Russell Senior <russell@personaltelco.net> Signed-off-by: David Bauer <mail@david-bauer.net>
* generic: kernel 5.4: fix probe error for AR803x PHYsDavid Bauer2021-06-131-1/+1
| | | | | | | | | | | | | | | | | | | Atheros PHYs using the at803x driver apart from the AR8031/AR8033 fail to probe with kernel 5.4, due to ret in at803x_probe being uninitialized. [ 1.403461] Atheros 8035 ethernet: probe of 4ef600c00.ethernet:01 failed with error -1066114012 Initialize ret in order to successfully prove the PHYs on kernel 5.4. Kernel 5.10 is not affected, as the ret is always assigned prior to returning. Tested on OCEDO Koala. Reported-by: Russell Senior <russell@personaltelco.net> Signed-off-by: David Bauer <mail@david-bauer.net>
* ramips: add support for TP-Link Archer C6 v3Amish Vishwakarma2021-06-135-180/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for the TP-Link Archer C6 v3 (FCC ID TE7A6V3) The patch adds identification changes to the existing TP-Link Archer A6, by Vinay Patil <post2vinay@gmail.com>, which has identical hardware. Specification ------------- MediaTek MT7621 SOC RAM: 128MB DDR3 SPI Flash: W25Q128 (16MB) Ethernet: MT7530 5x 1000Base-T WiFi 5GHz: Mediatek MT7613BE WiFi 2.4GHz: Mediatek MT7603E UART/Serial: 115200 8n1 Device Configuration & Serial Port Pins --------------------------------------- ETH Ports: LAN4 LAN3 LAN2 LAN1 WAN _______________________ | | Serial Pins: | VCC GND TXD RXD | |_____________________| LEDs: Power Wifi2G Wifi5G LAN WAN Build Output ------------ The build will generate following set of files [1] openwrt-ramips-mt7621-tplink_archer-c6-v3-initramfs-kernel.bin [2] openwrt-ramips-mt7621-tplink_archer-c6-v3-squashfs-factory.bin [3] openwrt-ramips-mt7621-tplink_archer-c6-v3-squashfs-sysupgrade.bin How to Use - Flashing from TP-Link Web Interface ------------------------------------------------ * Go to "Advanced/System Tools/Firmware Update". * Click "Browse" and upload the OpenWrt factory image: factory.bin[2] * Click the "Upgrade" button, and select "Yes" when prompted. TFTP Booting ------------ Setup a TFTP boot server with address 192.168.0.5. While starting U-boot press '4' key to stop autoboot. Copy the initramfs-kernel.bin[1] to TFTP server folder, rename as test.bin From u-boot command prompt run tftpboot followed by bootm. Recovery -------- Archer A6 V3 has recovery page activated if SPI booting from flash fails. Recovery page can be activated by powercycling the router four times before the boot process is complete. Note: TFTP boot can be activated only from u-boot serial console. Device recovery address: 192.168.0.1 Signed-off-by: Amish Vishwakarma <vishwakarma.amish@gmail.com> [fix indent] Signed-off-by: David Bauer <mail@david-bauer.net>
* rockchip: add NanoPi R4S supportTianling Shen2021-06-1012-2/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware -------- RockChip RK3399 ARM64 (6 cores) 4GB LPDDR4 RAM 2x 1000 Base-T 3 LEDs (LAN / WAN / SYS) 1 Button (Reset) Micro-SD slot 2x USB 3.0 Port Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card using dd. ===================================== NOTICE FOR USERS WHO USE 1GB VERSION: BY NOW IT IS NOT SUPPORTED ==================================== [initialed target] Co-developed-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Marty Jones <mj8263788@gmail.com> [fixed bootscript] Co-developed-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com> Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com> Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
* x86: add upgrade support to diag.shChris Blake2021-06-101-0/+4
| | | | | | | | | Similar to how this is done in the diag.sh found in the base-files package, we should blink our status LED (if we have one) during the upgrade process. This follows the same blink pattern as seen at ./package/base-files/files/etc/diag.sh#L36 Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 14:18:25 +0000