| Commit message (Collapse) | Author | Age | Files | Lines |
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The function mt7620_mdio_mode is only called once
and both the function and mdio_mode block have been named incorrectly,
leading to confusion and useless commits.
These lines in the mdio_mode block of mt7620_hw_init
are only intended for boards with an external mt7530 switch.
(see commit 194ca6127ee18cd3a95da4d03f02e43b5428c0bb)
Therefore, move lines from mdio_mode to the place in soc_mt7620.c
where the type of mt7530 switch is identified,
and move lines from mt7620_mdio_mode to a main function.
mt7620_mdio_mode was called from mt7620_gsw_init
where the priv struct is available,
so the lines must stay in mt7620_gsw_init function.
In order to keep things as simple as possible,
keep the DTS property related function calls together,
by moving them from mt7620_gsw_probe to init.
Remove the now useless DTS properties and extra phy nodes.
Fixes: 5a6229a93df8 ("ramips: remove superfluous & confusing DT binding")
Fixes: b85fe43ec8c4 ("ramips: mt7620: add force use of mdio-mode")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
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Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.
`md 0x10117014 1`
PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.
Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.
Also, added a kernel message to display the EPHY base address.
Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
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When the new variable ephy_base was introduced,
it was not applied to the if block for mdio_mode.
The first line in the mdio_mode if block
sets the EPHY base address to 12 in the SOC by writing a register,
but the corresponding variable in the driver
was still set to the default of 0.
This causes subsequent lines that write registers with the function
_mt7620_mii_write
to write to PHY addresses 0 through 4
while internal PHYs have been moved to addresses 12 through 16.
All of these lines are intended only for PHYs on the SOC internal switch,
however, they are being written to external ethernet switches
if they exist at those PHY addresses 0 through 4.
This causes some ethernet ports to be broken on boards with AR8327 or QCA8337 switch.
Other suggested fixes move those lines to the else block of mdio_mode,
but removing the else block completely also fixes it.
Therefore, move the lines to the mt7620_hw_init function main block,
and have only one instance of the function mtk_switch_w32
for writing the register with the EPHY base address.
In theory, this also allows for boards that have both external switches
and internal PHYs that lead to ethernet ports to be supported.
Fixes: 391df3782914 ("ramips: mt7620: add EPHY base mdio address changing possibility")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
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A workaround was added to the switch driver
to set SOC port 4 as an RGMII GMAC interface
based on the DTS property mediatek,port4-gmac.
(previously mediatek,port4)
However, the ethernet driver already does this,
but is being blocked by a return statement
whenever the phy-handle and fixed-link properties
are both missing from nodes that define the port properties.
Revert the workaround, so that both the switch driver
and ethernet driver are not doing the same thing
and move the phy-handle related lines down
so nothing is ending the function prematurely.
While at it, clean up kernel messages
and delete useless return statements.
Fixes: f6d81e2fa1f1 ("mt7620: gsw: make IntPHY and ExtPHY share mdio addr 4 possible")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
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These nodes are used for configuring a GMAC interface
and for defining external PHYs to be accessed with MDIO.
None of this is possible on MT7620N, only MT7620A,
so remove them from all MT7620N DTS.
When the mdio-bus node is missing, the driver returns -NODEV
which causes the internal switch to not initialize.
Replace that return so that everything works without the DTS node.
Also, an extra kernel message to indicate for all error conditions
that mdio-bus is disabled.
Fixes: d482356322c9 ("ramips: mt7620n: add mdio node and disable port4 by default")
Fixes: aa5014dd1a58 ("ramips: mt7620n: enable port 4 as EPHY by default")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
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There are only 2 options in the driver
for the function of mt7620 internal switch port 4:
EPHY mode (RJ-45, internal PHY)
GMAC mode (RGMII, external PHY)
Let the DTS property be boolean instead of string
where EPHY mode is the default.
Fix how the properties are written
for all DTS that use them,
and add missing nodes where applicable,
and remove useless nodes,
and minor DTS formatting.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
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The RTL8380-RTL9300 switches only forward packets when VLAN ID 1 is
configured. Do not use the standard failsafe configuration for DSA
accessing the default port directly, but configure a switch on the lan1
interface instead.
This will add the VLAN ID 1 configuration to the switch:
$ bridge vlan show
port vlan-id
lan1 1 PVID Egress Untagged
switch 1 PVID Egress Untagged
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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user port
Without this patch we have to manually bring up the CPU interface in
failsafe mode.
This was backported from kernel 5.12.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Tested-by: Rafał Miłecki <rafal@milecki.pl>
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These are the latest patches that just landed upstream for 5.13, will be
backported by Greg into 5.10 (because of stable@), and are now in the
5.4 backport branch of wireguard: https://git.zx2c4.com/wireguard-linux/log/?h=backport-5.4.y
Cc: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Tested-by: Stijn Segers <foss@volatilesystems.org>
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Add the new symbol to the generic kconfig.
No deleted or manually refreshed patches.
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
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Fixes the buffer and packet length calculations for Ethernet TX on
the RTL8380 SoC when CRC calculation offload is enabled.
CRC-offload is always done by the SoC, but additional CRC
calculation was previously done also by the kernel.
It also fixes detection of the DSA tag for packets on RTL8390
SoCs for ports > 28.
v2 has correct whitespace
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
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This fixes traffic stalls after ifdown & ifup.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Fixes commit 7b8931678c36 ("ath79: add gpio-latch driver for MikroTik RouterBOARDs")
Signed-off-by: David Bauer <mail@david-bauer.net>
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Currently, the option to disable subpage writing is only set
when a HW ECC engine is used.
Some boards lack a HW ECC engine and use software for that.
In this case, this NAND option does not get set when the NAND chip
does not support it, resulting in mounting errors.
Move the setting of this option to a generic init location so it
gets set for all types where required.
While at it, also OR the option instead of just setting it
so we don't overwrite potential flags being set somewhere else.
Before:
[ 1.681273] UBI: auto-attach mtd2
[ 1.684669] ubi0: attaching mtd2
[ 1.688877] ubi0 error: validate_ec_hdr: bad VID header offset 2048, expected 512
[ 1.696469] ubi0 error: validate_ec_hdr: bad EC header
[ 1.701712] Erase counter header dump:
[ 1.705512] magic 0x55424923
[ 1.709322] version 1
[ 1.712330] ec 1
[ 1.715331] vid_hdr_offset 2048
[ 1.718610] data_offset 4096
[ 1.721880] image_seq 1462320675
[ 1.725680] hdr_crc 0x12255a15
After:
1.680917] UBI: auto-attach mtd2
[ 1.684308] ubi0: attaching mtd2
[ 2.954504] random: crng init done
[ 3.142813] ubi0: scanning is finished
[ 3.163455] ubi0: attached mtd2 (name "ubi", size 124 MiB)
[ 3.169069] ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
[ 3.176037] ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
[ 3.182942] ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
[ 3.190013] ubi0: good PEBs: 992, bad PEBs: 0, corrupted PEBs: 0
[ 3.196102] ubi0: user volume: 3, internal volumes: 1, max. volumes count: 128
[ 3.203434] ubi0: max/mean erase counter: 2/0, WL threshold: 4096, image sequence number: 1462320675
[ 3.212700] ubi0: available PEBs: 0, total reserved PEBs: 992, PEBs reserved for bad PEB handling: 20
[ 3.222124] ubi0: background thread "ubi_bgt0d" started, PID 317
[ 3.230246] block ubiblock0_1: created from ubi0:1(rootfs)
[ 3.235819] ubiblock: device ubiblock0_1 (rootfs) set to be root filesystem
[ 3.256830] VFS: Mounted root (squashfs filesystem) readonly on device 254:0.
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
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This board has been supported in the ar71xx.
Links:
* https://mikrotik.com/product/RB912UAG-2HPnD
* https://openwrt.org/toh/hwdata/mikrotik/mikrotik_rb912uag-2hpnd
This also supports the 5GHz flavour of the board.
Hardware:
* SoC: Atheros AR9342,
* RAM: DDR 64MB,
* SPI NOR: 64KB,
* NAND: 128MB,
* Ethernet: x1 10/100/1000 port with passive POE in,
* Wi-Fi: 802.11 b/g/n,
* PCIe,
* USB: 2.0 EHCI controller, connected to mPCIe slot and a Type-A
port -- both can be used for LTE modem, but only one can be
used at any time.
* LEDs: 5 general purpose LEDs (led1..led5), power LED, user LED,
Ethernet phy LED,
* Button,
* Beeper.
Not working:
* Button: it shares gpio line 15 with NAND ALE and NAND IO7,
and current drivers doesn't easily support this configuration,
* Beeper: it is connected to bit 5 of a serial shift register
(tested with sysfs led trigger timer). But kmod-gpio-beeper
doesn't work -- we left this as is for now.
Flashing:
* Use the RouterBOARD Reset button to enable TFTP netboot,
boot kernel and initramfs and then perform sysupgrade.
* From ar71xx OpenWrt firmware run:
$ sysupgrade -F /tmp/<sysupgrade.bin>
For more info see: https://openwrt.org/toh/mikrotik/common.
Co-Developed-by: Koen Vandeputte <koen.vandeputte@citymesh.com>
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
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Main part is copied from ar71xx original driver rb91x_nand
written by Gabor Juhos <juhosg@openwrt.org>.
What is done:
* Support of kernel 5.4 and 5.10,
* DTS support,
* New gpio API (gpiod_*) support.
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
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This is a slighty modified version of ar71xx gpio-latch driver
written by Gabor Juhos <juhosg@openwrt.org>.
Changes:
* DTS support,
* New gpio API (gpiod_*).
Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Signed-off-by: Denis Kalashnikov <denis281089@gmail.com>
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All bcm4908 devices are expected to have GPIO buttons to make relevant
package selected by default.
This "fixes" triggering failsafe mode.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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* only add factory.bin when it's defined
* fix check-size vs. append-metadata
* whitespace/line break cleanup
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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* Remove micro-DTSI mt7621_dlink_dir-882-x1.dtsi to ease reading
config without too much inheritance
* Use "separate" partitioning DTSIs so we can use the partitioning
without a complete match on the other settings (i.e. without the
former parent DTSI)
* Rename files to express the new organization
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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The option was added in 5.9 and for some reason, it is causing performance
issues at least on an APU2 board with the igb device.
Switch CONFIG_PCIE_BUS_DEFAULT to fix the performance issues and match the
older kernel's behavior
Signed-off-by: Felix Fietkau <nbd@nbd.name>
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This reduces the flash space impact, since built-in code is much smaller
than a bunch of kernel modules on squashfs
Signed-off-by: Felix Fietkau <nbd@nbd.name>
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No deleted or manually refreshed patches.
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
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This patch failed to apply, breaking builds for the ramips target.
Fixes commit c44cefceb3ad ("generic: kernel 5.4: fix probe error for AR803x PHYs")
Signed-off-by: David Bauer <mail@david-bauer.net>
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These are architecture independent, so move them to generic config.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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Mark it as testing for now.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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Dumb copy of current kernel 5.4 config and patches.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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Recent filtering rules alow to trim the kernel configuration in size, do
that to reduce the diff between current config and upcoming one.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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Specifications:
- QCA9533 SoC, 8 MB nor flash, 64 MB DDR2 RAM
- 2x2 9dBi antenna, wifi 2.4Ghz 300Mbps
- 4x Ethernet LAN 10/100, 1x Ethernet WAN 10/100
- 1x WAN, LAN, Wifi, PWR, WPS, RE Leds
- Reset, Wifi on/off, WPS, RE buttons
- Serial UART at J4 onboard: 3.3v GND RX TX, 1152008N1
Label MAC addresses based on vendor firmware:
LAN *:ea label
WAN *:eb label +1
2.4 GHz *:ea label
The label MAC address in found in u-boot 0x1fc00
Installation:
Upload openwrt-ath79-generic-tplink_tl-wr841hp-v3-squashfs-factory.bin
from stock firmware webgui.
Maybe we need rename to shorten file name due to stock webgui error.
Revert back to stock firmware instructions:
- set your PC to static IP address 192.168.0.66 netmask 255.255.255.0
- download stock firmware from Tp-link website
- put it in the root directory of tftp server software
- rename it to wr841hpv3_tp_recovery.bin
- power on while pressing Reset button until any Led is lighting up
- wait for the router to reboot. done
Forum support topic:
https://forum.openwrt.org/t/support-for-tp-link-tl-wr841hp-v3-router
Signed-off-by: Andy Lee <congquynh284@yahoo.com>
[rebase and squash]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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This moves CONFIG_REGULATOR to the target config instead of the
subtarget config.
For kernel 5.10, CONFIG_AT803X_PHY depends on CONFIG_REGULATOR.
As we do not have a size constraint, move this symbol to the
target configuration for kernel 5.4 as well as 5.10.
Reported-by: Russell Senior <russell@personaltelco.net>
Signed-off-by: David Bauer <mail@david-bauer.net>
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Atheros PHYs using the at803x driver apart from the AR8031/AR8033 fail
to probe with kernel 5.4, due to ret in at803x_probe being
uninitialized.
[ 1.403461] Atheros 8035 ethernet: probe of 4ef600c00.ethernet:01
failed with error -1066114012
Initialize ret in order to successfully prove the PHYs on kernel 5.4.
Kernel 5.10 is not affected, as the ret is always assigned prior to
returning.
Tested on OCEDO Koala.
Reported-by: Russell Senior <russell@personaltelco.net>
Signed-off-by: David Bauer <mail@david-bauer.net>
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The patch adds support for the TP-Link Archer C6 v3 (FCC ID TE7A6V3)
The patch adds identification changes to the existing TP-Link Archer A6,
by Vinay Patil <post2vinay@gmail.com>, which has identical hardware.
Specification
-------------
MediaTek MT7621 SOC
RAM: 128MB DDR3
SPI Flash: W25Q128 (16MB)
Ethernet: MT7530 5x 1000Base-T
WiFi 5GHz: Mediatek MT7613BE
WiFi 2.4GHz: Mediatek MT7603E
UART/Serial: 115200 8n1
Device Configuration & Serial Port Pins
---------------------------------------
ETH Ports: LAN4 LAN3 LAN2 LAN1 WAN
_______________________
| |
Serial Pins: | VCC GND TXD RXD |
|_____________________|
LEDs: Power Wifi2G Wifi5G LAN WAN
Build Output
------------
The build will generate following set of files
[1] openwrt-ramips-mt7621-tplink_archer-c6-v3-initramfs-kernel.bin
[2] openwrt-ramips-mt7621-tplink_archer-c6-v3-squashfs-factory.bin
[3] openwrt-ramips-mt7621-tplink_archer-c6-v3-squashfs-sysupgrade.bin
How to Use - Flashing from TP-Link Web Interface
------------------------------------------------
* Go to "Advanced/System Tools/Firmware Update".
* Click "Browse" and upload the OpenWrt factory image: factory.bin[2]
* Click the "Upgrade" button, and select "Yes" when prompted.
TFTP Booting
------------
Setup a TFTP boot server with address 192.168.0.5.
While starting U-boot press '4' key to stop autoboot.
Copy the initramfs-kernel.bin[1] to TFTP server folder, rename as test.bin
From u-boot command prompt run tftpboot followed by bootm.
Recovery
--------
Archer A6 V3 has recovery page activated if SPI booting from flash fails.
Recovery page can be activated by powercycling the router four times
before the boot process is complete.
Note: TFTP boot can be activated only from u-boot serial console.
Device recovery address: 192.168.0.1
Signed-off-by: Amish Vishwakarma <vishwakarma.amish@gmail.com>
[fix indent]
Signed-off-by: David Bauer <mail@david-bauer.net>
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Hardware
--------
RockChip RK3399 ARM64 (6 cores)
4GB LPDDR4 RAM
2x 1000 Base-T
3 LEDs (LAN / WAN / SYS)
1 Button (Reset)
Micro-SD slot
2x USB 3.0 Port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card using
dd.
=====================================
NOTICE FOR USERS WHO USE 1GB VERSION:
BY NOW IT IS NOT SUPPORTED
====================================
[initialed target]
Co-developed-by: Marty Jones <mj8263788@gmail.com>
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[fixed bootscript]
Co-developed-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
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Similar to how this is done in the diag.sh found in the base-files
package, we should blink our status LED (if we have one) during the
upgrade process. This follows the same blink pattern as seen at
./package/base-files/files/etc/diag.sh#L36
Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
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The default trigger for the amber lights on lan1 and lan3 were
mistakenly swapped after the device's migration to DSA. This
caused activity on one port to trigger the amber light on the
other port. Swapping their default trigger in the DTS file
fixes that.
Signed-off-by: Adam Elyas <adamelyas@outlook.com>
[minor commit title adjustment, wrap commit message]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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At this moment kernel size in mt7620 snapshot builds is bigger than 2048k.
It should be disabled by default.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
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Since few months multiple users reported problems with various JBoot
devices. [0][1][2][3] All of them was bricked.
On my Lava LR-25G001 it freezes with current snapshot:
CDW57CAM_003 Jboot B695
Giga Switch AR8327 init
AR8327/AR8337 id ==> 0x1302
JRecovery Version R1.2 2014/04/01 18:25
SPI FLASH: MX25l12805d 16M
.
.
(freeze)
The kernel size is >2048k.
I built current master with minimal config and it boots well:
CDW57CAM_003 Jboot B695
Giga Switch AR8327 init
AR8327/AR8337 id ==> 0x1302
JRecovery Version R1.2 2014/04/01 18:25
SPI FLASH: MX25l12805d 16M
.
...........................
Starting kernel @80000000...
[ 0.000000] Linux version 5.4.124
Kernel size is <2048k.
Jboot bootloader isn't open source, so it's impossible to find
solution in code. It looks, that some buffer for kernel have 2MB size.
To avoid bricked devices, this commit introduces 2048k limit kernel
size for all jboot routers.
[0] https://bugs.openwrt.org/index.php?do=details&task_id=3539
[1] https://eko.one.pl/forum/viewtopic.php?pid=254344
[2] https://eko.one.pl/forum/viewtopic.php?id=20930
[3] https://eko.one.pl/forum/viewtopic.php?pid=241376#p241376
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
[remove Fixes:]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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Set the ethernet address from flash.
MAC addresses as verified by OEM firmware:
use interface source
2g wlan0 factory 0x04 (label)
LAN eth0.1 factory 0x28 (label+1)
WAN eth0.2 factory 0x2e (label+2)
Fixes: 671c9d16e382 ("ramips: add support for HILINK HLK-7628N")
Signed-off-by: Liu Yu <f78fk@live.com>
[drop old MAC address setup from 02_network, cut out state_default
changes, face-lift commit message, add Fixes:]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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The patch for adding the config_aneg function for the Atheros
AR8031/AR8033 PHY was formatted in a way it moved to different PHY
models while refreshing patches on kernel updates.
Move the diff directly below the PHY name so this won't happen in the
future.
Signed-off-by: David Bauer <mail@david-bauer.net>
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This enables autonegotiation for all ephy ports on probe.
Some devices do not configure the ports, particularly port 4.
Signed-off-by: Gaspare Bruno <gaspare@anlix.io>
[replace magic values ; reword commit message]
Signed-off-by: David Bauer <mail@david-bauer.net>
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The basic mode control register of the ESW PHYs is modified in this
codeblock. Use the respective macros to make this code more readable.
Signed-off-by: David Bauer <mail@david-bauer.net>
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As patches for the AR8031/AR8033 copper page selection were merged
upstream, we can backport these patches.
This also fixes a PHY capabilities detection issue on the Ubiquiti
ER-X-SFP.
Signed-off-by: David Bauer <mail@david-bauer.net>
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This replaces the register bits for RGMII delay on the MAC side in favor
of having the RGMII delay on the PHY side by setting the phy-mode
property to rgmii-id (RGMII internal delay), which is supported by the
at803x driver. Speed 1000 is fixed as a result, so now all ethernet
speeds function.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Michael Pratt <mcpratt@pm.me>
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The Ubiquiti Rocket 5AC Lite (R5AC-Lite) is an outdoor router.
Specifications:
- SoC: Qualcomm Atheros QCA9558
- RAM: 128 MB
- Flash: 16 MB SPI
- Ethernet: 1x 10/100/1000 Mbps
- WiFi 5 GHz: QCA988x
- Buttons: 1x (reset)
- LEDs: 1x power, 1x Ethernet, 4x RSSI
Installation:
- Instructions for XC-type Ubiquiti:
https://openwrt.org/toh/ubiquiti/common
Signed-off-by: Nick Hainke <vincent@systemli.org>
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NEC Aterm WF1200CR is a 2.4/5 GHz band 11ac (Wi-Fi 5) router, based on
QCA9561.
Specification:
- SoC : Qualcomm Atheros QCA9561
- RAM : DDR2 128 MiB (W971GG6SB-25)
- Flash : SPI-NOR 8 MiB (MX25L6433FM2I-08G)
- WLAN : 2.4/5 GHz 2T2R
- 2.4 GHz : QCA9561 (SoC)
- 5 GHz : QCA9888
- Ethernet : 2x 10/100 Mbps
- Switch : QCA9561 (SoC)
- LEDs/Keys : 8x/3x (2x buttons, 1x slide-switch)
- UART : through-hole on PCB
- JP1: Vcc, GND, NC, TX, RX from "JP1" marking
- 115200n8
- Power : 12 VDC, 0.9 A
Flash instruction using factory image (stock: < v1.3.2):
1. Boot WF1200CR normally with "Router" mode
2. Access to "http://192.168.10.1/" and open firmware update page
("ファームウェア更新")
3. Select the OpenWrt factory image and click update ("更新") button to
perform firmware update
4. Wait ~150 seconds to complete flashing
Alternate flash instruction using initramfs image (stock: >= v1.3.2):
1. Prepare the TFTP server with the IP address 192.168.1.10 and place
the OpenWrt initramfs image to the TFTP directory with the name
"0101A8C0.img"
2. Connect serial console to WF1200CR
3. Boot WF1200CR and interrupt with any key after the message
"Hit any key to stop autoboot: 2", the U-Boot starts telnetd after
the message "starting telnetd server from server 192.168.1.1"
4. login the telnet (address: 192.168.1.1)
5. Perform the following commands to modify "bootcmd" variable
temporary and check the value
(to ignore the limitation of available commands, "tp; " command at
the first is required as dummy, and the output of "printenv" is
printed on the serial console)
tp; set bootcmd 'set autostart yes; tftpboot'
tp; printenv
6. Save the modified variable with the following command and reset
device
tp; saveenv
tp; reset
7. The U-Boot downloads initramfs image from TFTP server and boots it
8. On initramfs image, download the sysupgrade image to the device and
perform the following commands to erase stock firmware and sysupgrade
mtd erase firmware
sysupgrade <sysupgrade image>
9. After the rebooting by completion of sysupgrade, start U-Boot telnetd
and login with the same way above (3, 4)
10. Perform the following commands to reset "bootcmd" variable to the
default and reset the device
tp; run seattle
tp; reset
(the contents of "seattle":
setenv bootcmd 'bootm 0x9f070040' && saveenv)
11. Wait booting-up the device
Known issues:
- the following 6x LEDs are connected to the gpio controller on QCA9888
chip and the implementation of control via the controller is missing in
ath10k/ath10k-ct
- "ACTIVE" (Red/Green)
- "2.4GHz" (Red/Green)
- "5GHz" (Red/Green)
Note:
- after the version v1.3.2 of stock firmware, "offline update" by
uploading image by user is deleted and the factory image cannot be
used
- the U-Boot on WF1200CR doesn't configure the port-side LEDs on WAN/LAN
and the configuration is required on OpenWrt
- gpio-hog: set the direction of GPIO 14(WAN)/19(LAN) to output
- pinmux: set GPIO 14/19 as switch-controlled LEDs
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
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The SERCOMM NA502 is a smart home gateway manufactured by SERCOMM and sold
under different brands (among others, A1 Telekom Austria SmartHome
Gateway). It has multi-protocol radio support in addition to LAN and WiFi.
Note: BLE is currently unsupported.
Specifications
--------------
- MT7621ST 880MHz, Single-Core, Dual-Thread
- MT7603EN 2.4GHz WiFi
- MT7662EN 5GHz WiFi + BLE
- 128MiB NAND
- 256MiB DDR3 RAM
- SD3503 ZWave Controller
- EM357 Zigbee Coordinator
MAC address assignment
----------------------
LAN MAC is read from the config partition, WiFi 2.4GHz is LAN+2 and matches
the OEM firmware. WiFi 5GHz with LAN+1 is an educated guess since the
OEM firmware does not enable 5GHz WiFi.
Installation
------------
Attach serial console, then boot the initramfs image via TFTP.
Once inside OpenWrt, run sysupgrade -n with the sysupgrade file.
Attention: The device has a dual-firmware design. We overwrite kernel2,
since kernel1 contains an automatic recovery image.
If you get NAND ECC errors and are stuck with bad eraseblocks, try to
erase the mtd partition first with
mtd unlock ubi
mtd erase ubi
This should only be needed once.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
[use kiB for IMAGE_SIZE]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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The compatible is a literal string without any problematic
characters, so there is no reason to quote it.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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Globalscale SheevaPlug:
* Marvell Kirkwood 88F6281
* 512 MB SDRAM
* 512 MB Flash
* Gigabit Network
* USB 2.0
* SD slot
* Serial console
The device is supported in mainline uboot/linux the commit adds only
some openwrt config for building an image.
Installation:
1 - Update uboot:
setenv ipaddr '192.168.0.111'
setenv serverip '192.168.0.1'
tftpboot u-boot.kwb
nand erase 0x0 0x100000
nand write 0x800000 0x0 0x100000
reset
2 - Install OpenWRT:
setenv ethaddr 00:50:43:01:xx:xx
saveenv
setenv ipaddr '192.168.0.111'
setenv serverip '192.168.0.1'
tftpboot openwrt-kirkwood-globalscale_sheevaplug-squashfs-factory.bin
nand erase.part ubi
nand write 0x800000 ubi 0x600000
reset
Signed-off-by: BERENYI Balazs <balazs@wee.hu>
Reviewed-by: Pawel Dembicki <paweldembicki@gmail.com>
[add vendor name for uboot-kirkwood, merge patches, copy to 5.10,
add AUTORELEASE for uboot-kirkwood, refresh patches]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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About the device
----------------
SoC: MediaTek MT7620a @ 580MHz
RAM: 64M
FLASH: 8MB
WiFi: SoC-integrated: MediaTek MT7620a bgn
WiFi: MediaTek MT7612EN nac
GbE: 2x (RTL8211F)
BTN: - WPS
- Reset
- Router/Repeater/AP (3-way slide-switch)
LED: - WPS (blue)
- 3-segment Wifi signal representation (blue)
- WiFi (blue)
- WAN (blue)
- LAN (blue)
- Power (blue)
UART: UART is present as Pads with through-holes on the PCB. They are
located next to the reset button and are labelled Vcc/TX/RX/GND as
appropriate. Use 3.3V, 57600-8N1.
Installation
------------
Using the webcmd interface
--------------------------
Warning: Do not update to the latest Wavlink firmware (version
20201201) as this removes the webcmd console and you will need to
use the serial port instead.
You will need to have built uboot/sqauashfs image for this device,
and you will need to provide an HTTP service where the image can
be downloaded from that is accessible by the device.
You cannot use the device manufacturers firmware upgrade interface
as it rejects the OpenWrt image.
1. Log into the device's admin portal. This is necessary to
authenticate you as a user in order to be able to access the
webcmd interface.
2. Navigate to http://<device-ip>/webcmd.shtml - you can access
the console directly through this page, or you may wish to
launch the installed `telnetd` and use telnet instead.
* Using telnet is recommended since it provides a more
convenient shell interface that the web form.
* Launch telnetd from the form with the command `telnetd`.
* Check the port that telnetd is running on using
`netstat -antp|grep telnetd`, it is likely to be 2323.
* Connect to the target using `telnet`. The username should
be `admin2860`, and the password is your admin password.
3. On the target use `curl` to download the image.
e.g. `curl -L -O http://<some-other-lan-ip>/openwrt-ramips-mt7620-\
wavlink_wl-wn579x3-squashfs-sysupgrade.bin`.
Check the hash using `md5sum`.
4. Use the mtd_write command to flash the image.
* The flash partition should be mtd4, but check
/sys/class/mtd/mtd4/name first. The partition should be
called 'Kernel'.
* To flash use the following command:
`mtd_write -r -e /dev/mtd<n> write <image-file> /dev/mtd<n>`
Where mtd<n> is the Kernel partition, and <image-file> is
the OpenWrt image previously downloaded.
* The command above will erase, flash and then reboot the
device. Once it reboots it will be running OpenWrt.
Connect via ssh to the device at 192.168.1.1 on the LAN port.
The WAN port will be configured via DHCP.
Using the serial port
---------------------
The device uses uboot like many other MT7260a based boards. To
use this interface, you will need to connect to the serial
interface, and provide a TFTP server. At boot follow the
bootloader menu and select option 2 to erase/flash the image.
Provide the address and filename details for the tftp server.
The bootloader will do the rest.
Once the image is flashed, the board will boot into OpenWrt. The
console is available over the serial port.
Signed-off-by: Ben Gainey <ba.gainey@googlemail.com>
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This patch adds support for the Devolo dLAN pro 1200+ WiFi ac.
This device is a plc wifi AC2400 router/extender with 2 Ethernet ports,
has a QCA7500 PLC and uses the HomePlug AV2 standard.
Other than the PLC the hardware is identical to the Devolo Magic 2 WIFI.
Therefore it uses the same dts, which was moved to a dtsi to be included
by both boards.
This is a board that was previously included in the ar71xx tree.
Hardware:
SoC: AR9344
CPU: 560 MHz
Flash: 16 MiB (W25Q128JVSIQ)
RAM: 128 MiB DDR2
Ethernet: 2xLAN 10/100/1000
PLC: QCA75000 (Qualcomm HPAV2)
PLC Uplink: 1Gbps MIMO
PLC Link: RGMII 1Gbps (WAN)
WiFi: Atheros AR9340 2.4GHz 802.11bgn
Atheros AR9882-BR4A 5GHz 802.11ac
Switch: QCA8337, Port0:CPU, Port2:PLC, Port3:LAN1, Port4:LAN2
Button: 3x Buttons (Reset, wifi and plc)
LED: 3x Leds (wifi, plc white, plc red)
GPIO Switch: 11-PLC Pairing (Active Low)
13-PLC Enable
21-WLAN power
MACs Details verified with the stock firmware:
Radio1: 2.4 GHz &wmac *:4c Art location: 0x1002
Radio0: 5.0 GHz &pcie *:4d Art location: 0x5006
Ethernet ðernet *:4e = 2.4 GHz + 2
PLC uplink --- *:4f = 2.4 GHz + 3
Label MAC address is from PLC uplink
The Powerline (PLC) interface of the dLAN pro 1200+ WiFi ac requires 3rd
party firmware which is not available from standard OpenWrt package
feeds. There is a package feed on github which you must add to
OpenWrt buildroot so you can build a firmware image which supports the
plc interface.
See: https://github.com/0xFelix/dlan-openwrt (forked from Devolo and
added compatibility for OpenWrt 21.02)
Flash instruction (TFTP):
1. Set PC to fixed ip address 192.168.0.100
2. Download the sysupgrade image and rename it to uploadfile
3. Start a tftp server with the image file in its root directory
4. Turn off the router
5. Press and hold Reset button
6. Turn on router with the reset button pressed and wait ~15 seconds
7. Release the reset button and after a short time
the firmware should be transferred from the tftp server
8. Allow 1-2 minutes for the first boot.
Signed-off-by: Felix Matouschek <felix@matouschek.org>
[add "plus" to compatible and device name]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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