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* realtek: add Linux Kernel 5.15 as testing versionINAGAKI Hiroshi2022-12-151-0/+1
| | | | | | | | | | | | | | | | Add Linux Kernel 5.15 support for testing. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [APRESIA ApresiaLightGS120GT-SS, Panasonic Switch-M24eG PN28240K, Switch-M48eG PN28480K] Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> TP-Link TL-SG2008P Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [D-Link DGS-1210-20, DGS-1210-52, Zyxel XGS1010-12] Tested-by: Markus Stockhausen <markus.stockhausen@gmx.de> [Zyxel XGS1250-12] Tested-by: Lucian Cristian <lucian.cristian@gmail.com> # Zyxel [HPE 1920-8G, 1920-48G] Tested-by: Jan Hoffmann <jan@3e8.eu>
* realtek: enable needs_standalone_vlan_filtering on DSA driver in 5.15INAGAKI Hiroshi2022-12-151-0/+1
| | | | | | | To configure VLAN 0, enable needs_standalone_vlan_filtering option of dsa_switch struct. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: update dsa.c of DSA driver for 5.15INAGAKI Hiroshi2022-12-151-101/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - rtl83xx_vlan_filtering() "struct switchdev_trans *trans" parameter was removed[1] and "struct netlink_ext_ack *extack" was added[2]. [1]: https://www.spinics.net/lists/netdev/msg712250.html [2]: https://www.spinics.net/lists/netdev/msg722496.html - rtl83xx_vlan_add/del() vlan->vid_begin and vlan->vid_end were removed and vlan->vid was added[3]. [3]: https://www.spinics.net/lists/netdev/msg712248.html - rtl83xx_vlan_prepare() "port_vlan_prepare" member was removed from "dsa_switch_ops" struct in dsa.h[4] and vlan_prepare function should be called from vlan_add function. Also, change return type of vlan_add function to int. [4]: https://www.spinics.net/lists/netdev/msg712252.html - rtl83xx_port_mdb_add() "port_mdb_prepare" member in "dsa_switch_ops" struct was removed and preparation need to be done in the function of "port_mdb_add" member instead. And also, int type need to be returned on "port_mdb_add" member[5]. [5]: https://www.spinics.net/lists/netdev/msg712251.html - rtl83xx_port_pre_bridge_flags(), rtl83xx_port_bridge_flags() The current "port_pre_bridge_flags" member and "port_bridge_flags" member in "dsa_switch_ops" in dsa.h has flags of "struct switchdev_brport_flags" type instead[6], so adjust to it. And, the changed features are passed by flags.mask[7] in rtl83xx_port_bridge_flags(), so check it before calling function to enable/disable fieature. [6]: https://lore.kernel.org/lkml/20210212151600.3357121-7-olteanv@gmail.com/ [7]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e18f4c18ab5b0dd47caaf8377c2e36d66f632a8c Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [shorten final return statement of rtl83xx_port_mdb_add()] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: update platform support for 5.15INAGAKI Hiroshi2022-12-152-6/+2
| | | | | | | | | | - fw_passed_dtb and others were replaced to get_fdt() function[1] - __appended_dtb defined by asm/bootinfo.h[2] [1]: https://www.spinics.net/lists/linux-mips/msg03332.html [2]: https://www.spinics.net/lists/linux-mips/msg03332.html Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: refresh config-5.15 in all subtargetsINAGAKI Hiroshi2022-12-154-92/+123
| | | | | | Refresh config-5.15 in all subtargets by kernel_menuconfig. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: refresh patches in 5.15INAGAKI Hiroshi2022-12-1532-126/+121
| | | | | | Adjust patches for kernel 5.15. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: drop patches of upstreamed fix and changes from 5.15INAGAKI Hiroshi2022-12-154-1113/+0
| | | | | | | | | | - 007-5.16-gpio-realtek...: upstreamed on 5.16 and backported to 5.15.3 - 708-brflood-spi.patch : upstreamed - 709-lag-offloading.patch: upstreamed - 713-v5.12-net-dsa-... : upstreamed and some implementations are replaced Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: drop patches of upstreamed drivers from 5.15INAGAKI Hiroshi2022-12-156-1091/+0
| | | | | | | | | | | The following drivers were upstreamed and available on 5.15, so drop from OpenWrt tree. - realtek-otto-gpio (5.13) - realtek-rtl-spi (5.12) - realtek-rtl-intc (5.12) Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: copy dts/files/patches/configs for 5.15INAGAKI Hiroshi2022-12-15139-0/+39485
| | | | | | | | Copy dts/files/patches/configs from 5.10 to 5.15. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [refresh with updated DGS-1210 dts files] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: update GPIO bindings for DGS-1210-10PJan-Niklas Burfeind2022-12-091-4/+26
| | | | | | | | | | | | | | | | add three missing LEDs - PoE-Max - Link/Act - PoE add two missing buttons - mode - reset The last was dropped in commit 61a3d0075b15 ("realtek: update GPIO bindings in the dts files in dts-5.10") Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
* realtek: d-link: add support for dgs-1210-28mp-fAndreas Böhler2022-12-084-90/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General hardware info: ---------------------- D-Link DGS-1210-28MP rev. F1 is a switch with 24 ethernet ports and 4 combo ports, all ports Gbit capable. It is based on a RTL8382 SoC @ 500MHz, DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE capable with a total PoE power budget of 370W. Power over Ethernet: -------------------- The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports each. They are controlled by a Nuvoton MCU. In order to enable PoE, the realtek-poe package is required. It is installed by default, but currently it requires the manual editing of /etc/config/poe. Keep in mind that the port number assignment does not match on this switch, alway 8 ports are in reversed order: 8-1, 16-9 and 24-17. LEDs and Buttons: ----------------- On stock firmware, the mode button is supposed to switch the LED indicators of all port LEDs between Link Activity and PoE status. The currently selected mode is visualized using the respective LEDs. PoE Max indicates that the maximum PoE budget has been reached. Since there is currently no support for this behavior, these LEDs and the mode button can be used independently. Serial connection: ------------------ The UART for the SoC (115200 8N1) is available via unpopulated standard 0.1" pin header marked J6. Pin1 is marked with arrow and square. Pin 1: Vcc 3.3V Pin 2: Tx Pin 3: Rx Pin 4: Gnd OEM installation from Web Interface: ------------------------------------ 1. Make sure you are booting using OEM in image 2 slot. If not, switch to image2 using the menus System > Firmware Information > Boot from image2 Tools > reboot 2. Upload image in vendor firmware via Tools > Backup / Upgrade Firmware > image1 3. Toogle startup image via System > Firmware Information > Boot from image1 4. Tools > reboot Other installation methods not tested, but since the device shares the board with the DGS-1210-28, the following should work: Boot initramfs image from U-Boot: --------------------------------- 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. Press CTRL+C keys to get into real U-Boot prompt 3. Init network with `rtk network on` command 4. Load image with `tftpboot 0x8f000000 openwrt-rtl838x-generic-d-link_dgs-1210-28mp-f-initramfs-kernel.bin` command 5. Boot the image with `bootm` command Signed-off-by: Andreas Böhler <dev@aboehler.at>
* realtek: fix dell typoJan-Niklas Burfeind2022-12-011-3/+3
| | | | | | | should be add/delete or abbreviated add/del Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* realtek: refactor keep vlan tag setup, fix tagged forwardingLuiz Angelo Daros de Luca2022-12-017-23/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in dsa.c:rtl83xx_port_enable() was trying to set vlan_port_tag_sts_ctrl while dealing with differences between SoCs. However, not only that register has a different address, the register structure and even the 2-bit value semantic changes for each SoC. The vlan_port_tag_sts_ctrl field was dropped and converted into a vlan_port_keep_incoming_tag_set() function that abstracts the different between SoCs. The macro referencing that register migrated to the SoC specific c file as it will be privately used by each file. All magic numbers were converted into macros using BITMASK and FIELD_PREP. The vlan_port_tag_sts_ctrl debugfs was dropped for now as it is already broken for rtl93xx. The best place for SoC specific code might be in each respective c file and not in if/else clauses. The final result is: rtl838x: set ITAG_STS=TAGGED, same as before rtl839x: set ITAG_STS=TAGGED instead of IGR_P_ITAG_KEEP=0x1, fixing forwarding of tagged packets rtl930x: set EGR_ITAG_STS=TAGGED instead of IGR_P_ITAG=0x1, possibly fixing forwarding of tagged packets rtl931x: set EGR_ITAG_STS=TAGGED instead of OTPID_KEEP=0x1, possibly fixing forwarding of tagged packets Without (EGR_)ITAG_STS=TAGGED, at least for rtl839x, forwarded packets will drop the vlan tag while packets from the CPU will still have the correct tag. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
* realtek: Fix rtl930x speed status accessorOlliver Schinagl2022-12-011-3/+3
| | | | | | | | | | | | | | The rtl930x speed status registers require 4 bits to indicate the speed status. As such, we want to divide by 8. To make things consistent with the rest of this code, use a bitshift however. This bug probably won't affect many users yet, as there aren't many rtl930x switches in the wild yet with more then 10 ports, and thus a low-impact bugfix. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> [also fix port field extraction] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix typo in debug messageLuiz Angelo Daros de Luca2022-11-051-2/+2
| | | | | | vid_end was mentioned twice. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
* realtek: mark clock source as continuousSander Vanheule2022-11-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | After replacing the R4K event timer and clock source with the new Realtek Otto timer, performance for RTL839x devices was severely impacted, as reported by Hiroshi. Research by Markus showed that after commit 4657a5301eb5 ("realtek: avoid busy waiting for RTL839x PHY read/write"), the ethernet driver could only update a phy once per timer interval, which also heavily impacted boot time. On e.g. a Zyxel GS1900-48, this added around a minute to the time to fully initialise the switch. By marking the otto clocksource as continuous, the kernel enables it to be used for high resolution timers. This allows readx_poll_timeout() to sleep for less than one system timer interval, reducing system dead time. Link: https://github.com/openwrt/openwrt/issues/11117 Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com> Cc: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
* target/realtek: use netif_receive_skb_listRosen Penev2022-11-011-1/+4
| | | | | | Small performance improvement on rx. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* realtek: Fix CRC offloading for rtl83xxOlliver Schinagl2022-10-291-1/+1
| | | | | | | | | | | In rtl83xx_set_features we set bit 3 to enable, and bit 4 to disable checksuming. Looking at rtl93xx_set_features we however see that for both enable and disable the same bit is used (bit 4). This can't be right, especially as bit 4 for rtl83xx seems to be Collision threshold occupying 2 bits. Change this to make this more logical. Fixes: 9e8d62e42117 ("realtek: enable CRC offloading") Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
* realtek: use assisted learning on CPU portJan Hoffmann2022-10-262-0/+22
| | | | | | | | | | | | | | | | | | | | L2 learning on the CPU port is currently not consistently configured and relies on the default configuration of the device. On RTL83xx, it is disabled for packets transmitted with a TX header, as hardware learning corrupts the forwarding table otherwise. As a result, unneeded flooding of traffic for the CPU port can already happen on some devices now. It is also likely that similar issues exist on RTL93xx, which doesn't have a field to disable learning in the TX header. To address this, disable hardware learning for the CPU port globally on all devices. Instead, enable assisted learning to let DSA write FDB entries to the switch. For now, this does not sync local/bridge entries to the switch. However, support for that was added in Linux 5.14, so the next switch to a newer kernel version is going to fix this. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: set up L2 table entries properlyJan Hoffmann2022-10-261-10/+19
| | | | | | | | | | | | | | | | | | | | | | | Initialize the data structure using memset to avoid the possibility of writing garbage values to the hardware. Always set a valid entry type, which should fix writing unicast entries on RTL930x. For unicast entries, set the is_static flag to prevent the switch from aging them out. Also set the rvid field for unicast entries. This is not strictly necessary, as the switch fills it in automatically from a non-zero vid. However, this makes the code consistent with multicast entry setup. While at it, reorder the statements and fix some style issues (double space, comma instead of semicolon at end of statement). Also remove the unneeded priv parameter and debug print for the multicast entry setup function. Fixes: cde31976e37 ("realtek: Add support for Layer 2 Multicast") Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: 5.10: refresh kernel patchesChristian Marangi2022-10-251-1/+1
| | | | | | | | | Refresh kernel patches for realtek 5.10 kernel Refreshed patch: - 300-mips-add-rtl838x-platform.patch Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* realtek: consistently flood RMA framesSander Vanheule2022-10-231-30/+40
| | | | | | | | | | | | | | | | The switches support different actions for incoming ethernet multicast frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The current code will set the 2-bit action field to FLOOD (0x3) for most classes, but the highest bit is always unset for the relevant control registers. This means the DROP (0x1) action being used for these classes; whatever class the MSB happens to be in. For RTL838x, this results in {20,23-2F} frames being dropped, instead of flooding all ports. On other switch generations, {0F,1F,2F} frames are dropped. This is inconsistent, and appears to be a mistake. Remove this inconsistency by flooding all multicast frames with RMA addresses. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: remove RTL839x path in RTL838x multicastSander Vanheule2022-10-231-19/+14
| | | | | | | | | | | | | | The multicast setup function rtl838x_eth_set_multicast_list() checks if the current SoC is a RTL839x family device. However, the function is only included in the RTL838x ops table, so this path should never be taken, making this dead code. rtl839x_eth_set_multicast_list() is already present in the RTL839x ops table, so it should be safe to remove this branch. While touching the code, also re-sort the functions to match sorting elsewhere, with rtl838x coming before rtl839x. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: reduce excessive logging for FDB operationsJan Hoffmann2022-10-232-68/+3
| | | | | | | | | | | | Currently several messages at KERN_INFO level are printed for every FDB del/dump operation. This can cause a significant slowdown for example while using "bridge fdb", and may even trigger a watchdog. Remove most of these log messages, as the new L2 table debugfs node should be a good replacement. Change the remaining messages to KERN_DEBUG level. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: add debugfs node for L2 tableJan Hoffmann2022-10-231-0/+107
| | | | | | | This allows to view all unicast and multicast entries that are currently in the L2 hash table and the CAM. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: avoid busy waiting for RTL839x PHY read/writeJan Hoffmann2022-10-231-12/+33
| | | | | | | Switch to a polling implementation similar to the one for RTL838x, to allow other kernel tasks to run while waiting. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: disable otto timer for RTL93xx targetsMarkus Stockhausen2022-10-232-0/+2
| | | | | | | | | The new timer is not yet ready for all targets. Avoid interactive questions during build Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [rename symbol to CONFIG_REALTEK_OTTO_TIMER] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: timer driver: activate for RTL839X devicesMarkus Stockhausen2022-10-233-7/+12
| | | | | | | | | Use the new timer driver for the RTL839X devices and remove the no longer needed modules. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [correct timer compatible order, update selected symbols] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: timer driver: activate for RTL838X devicesMarkus Stockhausen2022-10-233-6/+14
| | | | | | | | | Use the new timer driver for the RTL838X devices. Remove the no longer needed modules. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [correct timer compatible order, update selected symbols] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: timer driver: documentationMarkus Stockhausen2022-10-231-0/+85
| | | | | | | | | Provide some helpful information about the devicetree configuration of our new driver Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [correct compatible order in examples] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: resurrect timer driverMarkus Stockhausen2022-10-232-0/+338
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we provide a clock driver for the Reltek SOCs the CPU frequency might change on demand. This has direct visible effects during operation - the CEVT 4K timer is no longer a stable clocksource - after CPU frequencies changes time calculation works wrong - sched_clock falls back to kernel default interval (100 Hz) - timestamps in dmesg have only 2 digits left [ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ... [ 0.060000] pid_max: default: 32768 minimum: 301 [ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build [ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ... Looking around where we can start the CEVT timer for RTL930X is a good basis. Initially it was developed as a clocksource driver for the broken timer in that specific SOC series. Afterwards it was shifted around to the CEVT location, got SMP enablement and lost its clocksource feature. So we at least have something to copy from. As the timers on these devices are well understood the implementation follows this way: - leave the RTL930X implementation as is - provide a new driver for RTL83XX devices only - swap RTL930X driver at a later time Like the clock driver this patch contains a self contained module that is SOC independet and already provides full support for the RTL838X, RTL839X and RTL930X devices. Some of the new (or reestablished) features are: - simplified initialization routines - SMP setup with CPU hotplug framework - derived from LXB clock speed - supplied clocksource - dedicated register functions for better readability - documentation about some caveats Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [remove unused header includes, remove old CONFIG_MIPS dependency, add REALTEK_ prefix to driver symbol] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: cleanup rtl83{8x,9x}_enable_learning/floodINAGAKI Hiroshi2022-10-082-44/+22
| | | | | | | | | | | | | In *_enable_learning() only address learning should be configured, so remove enabling forwarding. Forwarding is configured by the respective *_enable_flood() functions. Clean up both functions for RTL838x and RTL839x, and fix the comment on the number of entries. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [squash RTL838x, RTL839x changes] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: swap *_phylink_mac_link_down() contentsINAGAKI Hiroshi2022-10-081-7/+8
| | | | | | | | | Fix the (accidentally?) swapped contents of rtl83xx_phylink_mac_link_down() and rtl93xx_phylink_mac_link_down(). Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix place of fdb/mdb info messagesINAGAKI Hiroshi2022-10-081-2/+2
| | | | | | | | | Those messages should be printed when entry was found (idx >= 0). Move them to the right place to not print invalid entry indices. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amden commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add missing of.h include in phy driverINAGAKI Hiroshi2022-10-081-0/+1
| | | | | | | | of.h is required for of_property_read_u32(). Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix use of uninitialized sds_modeINAGAKI Hiroshi2022-10-081-2/+1
| | | | | | | | | The initial state of sds_mode in rtl9300_force_sds_mode() is null and it will be configured in switch-case. So print message after it. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: use MIPS fw_init_cmdline()INAGAKI Hiroshi2022-10-081-20/+2
| | | | | | | | | Use the generic function of MIPS in Linux Kernel instead of open coding our own initialisation. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: update SMP-related calls in prom_init()INAGAKI Hiroshi2022-10-081-6/+2
| | | | | | | | | | | | | | | | | | | | The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects this symbol, so the family check is redudant. Furthermore, mips_cm_probe() is already called from setup_arch() in mips/kernel/setup.c before prom_init(), and as such is not required. Also move mips_cpc_probe() to run just before registering SMP ops. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [squash SMP change commits, reword commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net> --- This patch only really has an impact on the rtl931x subtarget, which has no devices. Noboby is currently set up to test these patches either, but the end result is closer to MIPS_GENERIC, so I do not expect it to cause issues.
* realtek: separate lock of RTL8231 from phy driverINAGAKI Hiroshi2022-10-081-9/+10
| | | | | | | RTL8231 and ethernet phys are not on the same bus, so separate the lock to each own to cut off the unnecessary dependency. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* kernel: bump 5.10 to 5.10.146John Audia2022-10-021-1/+1
| | | | | | All patches automatically rebased. Signed-off-by: John Audia <therealgraysky@proton.me>
* realtek: use correct CAUSEF_DC macro in prom.cSander Vanheule2022-10-011-1/+1
| | | | | | | | The workaround for an already-enabled R4K timer used a non-existent macro CAUSE_DC. Fix compiling by using the actual macro CAUSEF_DC. Fixes: b7aab1958591 ("realtek: SMP handling of R4K timer interrupts") Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: SMP handling of R4K timer interruptsMarkus Stockhausen2022-10-011-3/+9
| | | | | | | | | | | | | | | | | | | Until now there has been no good explanation why we mess with the R4K timer on SMP. After extensive testing and looking at the SDK code it becomes clear what it is all about. When we disable the CEVT_R4K module (we will do with the new timer driver) the R4K timer hardware still fires interrupts on the secondary CPU. To get around this we have two options: - Disable IRQ 7 - Stop the counter completely This patch selects option two because this is the root of evil.. To be on the safe side we will do it only in case the CEVT_R4K module is disabled. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: fix SMP startupMarkus Stockhausen2022-10-011-2/+1
| | | | | | | | The scope of the SMP startup structure is wrong. It is created on the stack and not as a global variable. This can lead to startup failures. Fixes: 3f41360eb70c ("realtek: use upstream recommendation for CPU start") Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de
* realtek: Convert incorrect v5.10 patchesOlliver Schinagl2022-10-0127-1/+470
| | | | | | | | | | | | | | | | | OpenWRT's developer guide prefers having actual patches so they an be sent upstream more easily. However, in this case, Adding proper fields also allows for `git am` to properly function. Some of these patches are quite old, and lack much traceable history. This commit tries to rectify that, by digging in the history to find where and how it was first added. It is by no means perfect and also shows some patches that should have been long gone. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
* kernel: move kernel image cmdline hack to the octeon targetFelix Fietkau2022-09-301-14/+0
| | | | | | It is the only remaining user of this hack Signed-off-by: Felix Fietkau <nbd@nbd.name>
* realtek: rtl931x: fix missing CONFIG_COMMON_CLK_REALTEK config flagChristian Marangi2022-09-281-0/+1
| | | | | | | | | When the realtek clock driver was introduced, CONFIG_COMMON_CLK_REALTEK was not correctly disabled for other subtarget. Add the missing config flag to fix compilation error on buildbot. Fixes: 4850bd887c3a ("realtek: add RTL83XX clock driver") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* realtek: fix RTL839x egress tag for ports >= 32Jan Hoffmann2022-09-251-1/+1
| | | | | | | Don't overwrite AS_DPM and L2LEARNING flags when dest_port is >= 32. Fixes: 1773264a0c6d ("realtek: correct egress frame port verification") Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* kernel: bump 5.10 to 5.10.144John Audia2022-09-221-5/+5
| | | | | | All patches automatically rebased. Signed-off-by: John Audia <therealgraysky@proton.me>
* realtek: use upstream recommendation for secondary CPU startMarkus Stockhausen2022-09-182-26/+31
| | | | | | | | | | | Currently we fix interrupts/timers for the secondary CPU by patching vsmp_init_secondary(). Get a little bit more generic and use the upstream recommended way instead. Additionally avoid a check around register_cps_smp_ops() because it does that itself. See https://lkml.org/lkml/2022/9/12/522 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: avoid wrong interrupt routingMarkus Stockhausen2022-09-181-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interrupt controller depends on two control registers. GIMR enables or disables interrupts and IRRx routes these to MIPS CPU interrupts 2-7. Wiki currently states "A value of '0' (in IRRx) disconnects this input from the output line, independent of the line's setting in GIMR." Contrary to normal intuition this statement DOES NOT mean, that interrupts can be disabled by IRRx alone. The sad truth was discovered by enabling SMP for an Zyxel XGS1010 on the 930x target. It shows that driver and interrupts behave as follows: - Timer 0 interrupt 7 has active routing to CPU0 and no routing to CPU1 - Timer 1 interrupt 8 has no routing to CPU0 and active routing to CPU1 - Unmasking (enabling) interrupts writes 1 bits to all GIMR registers - Masking (disabling) interrupts writes 0 bits to both GIMR registers During operation we can encounter a situation like - GIMR bit for a interrupt/CPU combination is set to enabed (=1) - IRRx routing bits for a interrupt/CPU combination are set to disabed (=0) This setting already allows the hardware to fire interrupts to the target CPU/VPE if the other CPU/VPE is currently busy. Especially for CPU bound timer interrupts this is lethal. If timer interrupt 7 arrives at CPU1 and vice versa for interrupt 8 the restart trigger gets lost. The timer dies and a msleep() operation in the kernel will halt endlessly. Fix this by tracking the IRRx active routing setting in a new bitfield with 0="routing active" and 1="no routing". Enable interrupts in GIMR only for a interrupt & CPU if routing is active. Thus we have - GIMR = 0 / IRRx = 0 -> everything disabled - GIMR = 1 / IRRx > 0 -> active and normal routing - GIMR = 0 / IRRx > 0 -> masked (disabled) with normal routing - GIMR = 1 / IRRx = 0 -> no longer possible Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-09 16:58:55 +0000