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* realtek: mark clock source as continuousSander Vanheule2022-11-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | After replacing the R4K event timer and clock source with the new Realtek Otto timer, performance for RTL839x devices was severely impacted, as reported by Hiroshi. Research by Markus showed that after commit 4657a5301eb5 ("realtek: avoid busy waiting for RTL839x PHY read/write"), the ethernet driver could only update a phy once per timer interval, which also heavily impacted boot time. On e.g. a Zyxel GS1900-48, this added around a minute to the time to fully initialise the switch. By marking the otto clocksource as continuous, the kernel enables it to be used for high resolution timers. This allows readx_poll_timeout() to sleep for less than one system timer interval, reducing system dead time. Link: https://github.com/openwrt/openwrt/issues/11117 Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com> Cc: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
* target/realtek: use netif_receive_skb_listRosen Penev2022-11-011-1/+4
| | | | | | Small performance improvement on rx. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* realtek: Fix CRC offloading for rtl83xxOlliver Schinagl2022-10-291-1/+1
| | | | | | | | | | | In rtl83xx_set_features we set bit 3 to enable, and bit 4 to disable checksuming. Looking at rtl93xx_set_features we however see that for both enable and disable the same bit is used (bit 4). This can't be right, especially as bit 4 for rtl83xx seems to be Collision threshold occupying 2 bits. Change this to make this more logical. Fixes: 9e8d62e42117 ("realtek: enable CRC offloading") Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
* realtek: use assisted learning on CPU portJan Hoffmann2022-10-262-0/+22
| | | | | | | | | | | | | | | | | | | | L2 learning on the CPU port is currently not consistently configured and relies on the default configuration of the device. On RTL83xx, it is disabled for packets transmitted with a TX header, as hardware learning corrupts the forwarding table otherwise. As a result, unneeded flooding of traffic for the CPU port can already happen on some devices now. It is also likely that similar issues exist on RTL93xx, which doesn't have a field to disable learning in the TX header. To address this, disable hardware learning for the CPU port globally on all devices. Instead, enable assisted learning to let DSA write FDB entries to the switch. For now, this does not sync local/bridge entries to the switch. However, support for that was added in Linux 5.14, so the next switch to a newer kernel version is going to fix this. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: set up L2 table entries properlyJan Hoffmann2022-10-261-10/+19
| | | | | | | | | | | | | | | | | | | | | | | Initialize the data structure using memset to avoid the possibility of writing garbage values to the hardware. Always set a valid entry type, which should fix writing unicast entries on RTL930x. For unicast entries, set the is_static flag to prevent the switch from aging them out. Also set the rvid field for unicast entries. This is not strictly necessary, as the switch fills it in automatically from a non-zero vid. However, this makes the code consistent with multicast entry setup. While at it, reorder the statements and fix some style issues (double space, comma instead of semicolon at end of statement). Also remove the unneeded priv parameter and debug print for the multicast entry setup function. Fixes: cde31976e37 ("realtek: Add support for Layer 2 Multicast") Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: 5.10: refresh kernel patchesChristian Marangi2022-10-251-1/+1
| | | | | | | | | Refresh kernel patches for realtek 5.10 kernel Refreshed patch: - 300-mips-add-rtl838x-platform.patch Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* realtek: consistently flood RMA framesSander Vanheule2022-10-231-30/+40
| | | | | | | | | | | | | | | | The switches support different actions for incoming ethernet multicast frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The current code will set the 2-bit action field to FLOOD (0x3) for most classes, but the highest bit is always unset for the relevant control registers. This means the DROP (0x1) action being used for these classes; whatever class the MSB happens to be in. For RTL838x, this results in {20,23-2F} frames being dropped, instead of flooding all ports. On other switch generations, {0F,1F,2F} frames are dropped. This is inconsistent, and appears to be a mistake. Remove this inconsistency by flooding all multicast frames with RMA addresses. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: remove RTL839x path in RTL838x multicastSander Vanheule2022-10-231-19/+14
| | | | | | | | | | | | | | The multicast setup function rtl838x_eth_set_multicast_list() checks if the current SoC is a RTL839x family device. However, the function is only included in the RTL838x ops table, so this path should never be taken, making this dead code. rtl839x_eth_set_multicast_list() is already present in the RTL839x ops table, so it should be safe to remove this branch. While touching the code, also re-sort the functions to match sorting elsewhere, with rtl838x coming before rtl839x. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: reduce excessive logging for FDB operationsJan Hoffmann2022-10-232-68/+3
| | | | | | | | | | | | Currently several messages at KERN_INFO level are printed for every FDB del/dump operation. This can cause a significant slowdown for example while using "bridge fdb", and may even trigger a watchdog. Remove most of these log messages, as the new L2 table debugfs node should be a good replacement. Change the remaining messages to KERN_DEBUG level. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: add debugfs node for L2 tableJan Hoffmann2022-10-231-0/+107
| | | | | | | This allows to view all unicast and multicast entries that are currently in the L2 hash table and the CAM. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: avoid busy waiting for RTL839x PHY read/writeJan Hoffmann2022-10-231-12/+33
| | | | | | | Switch to a polling implementation similar to the one for RTL838x, to allow other kernel tasks to run while waiting. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: disable otto timer for RTL93xx targetsMarkus Stockhausen2022-10-232-0/+2
| | | | | | | | | The new timer is not yet ready for all targets. Avoid interactive questions during build Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [rename symbol to CONFIG_REALTEK_OTTO_TIMER] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: timer driver: activate for RTL839X devicesMarkus Stockhausen2022-10-233-7/+12
| | | | | | | | | Use the new timer driver for the RTL839X devices and remove the no longer needed modules. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [correct timer compatible order, update selected symbols] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: timer driver: activate for RTL838X devicesMarkus Stockhausen2022-10-233-6/+14
| | | | | | | | | Use the new timer driver for the RTL838X devices. Remove the no longer needed modules. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [correct timer compatible order, update selected symbols] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: timer driver: documentationMarkus Stockhausen2022-10-231-0/+85
| | | | | | | | | Provide some helpful information about the devicetree configuration of our new driver Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [correct compatible order in examples] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: resurrect timer driverMarkus Stockhausen2022-10-232-0/+338
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we provide a clock driver for the Reltek SOCs the CPU frequency might change on demand. This has direct visible effects during operation - the CEVT 4K timer is no longer a stable clocksource - after CPU frequencies changes time calculation works wrong - sched_clock falls back to kernel default interval (100 Hz) - timestamps in dmesg have only 2 digits left [ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ... [ 0.060000] pid_max: default: 32768 minimum: 301 [ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) [ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build [ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ... Looking around where we can start the CEVT timer for RTL930X is a good basis. Initially it was developed as a clocksource driver for the broken timer in that specific SOC series. Afterwards it was shifted around to the CEVT location, got SMP enablement and lost its clocksource feature. So we at least have something to copy from. As the timers on these devices are well understood the implementation follows this way: - leave the RTL930X implementation as is - provide a new driver for RTL83XX devices only - swap RTL930X driver at a later time Like the clock driver this patch contains a self contained module that is SOC independet and already provides full support for the RTL838X, RTL839X and RTL930X devices. Some of the new (or reestablished) features are: - simplified initialization routines - SMP setup with CPU hotplug framework - derived from LXB clock speed - supplied clocksource - dedicated register functions for better readability - documentation about some caveats Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [remove unused header includes, remove old CONFIG_MIPS dependency, add REALTEK_ prefix to driver symbol] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: cleanup rtl83{8x,9x}_enable_learning/floodINAGAKI Hiroshi2022-10-082-44/+22
| | | | | | | | | | | | | In *_enable_learning() only address learning should be configured, so remove enabling forwarding. Forwarding is configured by the respective *_enable_flood() functions. Clean up both functions for RTL838x and RTL839x, and fix the comment on the number of entries. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [squash RTL838x, RTL839x changes] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: swap *_phylink_mac_link_down() contentsINAGAKI Hiroshi2022-10-081-7/+8
| | | | | | | | | Fix the (accidentally?) swapped contents of rtl83xx_phylink_mac_link_down() and rtl93xx_phylink_mac_link_down(). Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix place of fdb/mdb info messagesINAGAKI Hiroshi2022-10-081-2/+2
| | | | | | | | | Those messages should be printed when entry was found (idx >= 0). Move them to the right place to not print invalid entry indices. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amden commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add missing of.h include in phy driverINAGAKI Hiroshi2022-10-081-0/+1
| | | | | | | | of.h is required for of_property_read_u32(). Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix use of uninitialized sds_modeINAGAKI Hiroshi2022-10-081-2/+1
| | | | | | | | | The initial state of sds_mode in rtl9300_force_sds_mode() is null and it will be configured in switch-case. So print message after it. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: use MIPS fw_init_cmdline()INAGAKI Hiroshi2022-10-081-20/+2
| | | | | | | | | Use the generic function of MIPS in Linux Kernel instead of open coding our own initialisation. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: update SMP-related calls in prom_init()INAGAKI Hiroshi2022-10-081-6/+2
| | | | | | | | | | | | | | | | | | | | The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects this symbol, so the family check is redudant. Furthermore, mips_cm_probe() is already called from setup_arch() in mips/kernel/setup.c before prom_init(), and as such is not required. Also move mips_cpc_probe() to run just before registering SMP ops. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [squash SMP change commits, reword commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net> --- This patch only really has an impact on the rtl931x subtarget, which has no devices. Noboby is currently set up to test these patches either, but the end result is closer to MIPS_GENERIC, so I do not expect it to cause issues.
* realtek: separate lock of RTL8231 from phy driverINAGAKI Hiroshi2022-10-081-9/+10
| | | | | | | RTL8231 and ethernet phys are not on the same bus, so separate the lock to each own to cut off the unnecessary dependency. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* kernel: bump 5.10 to 5.10.146John Audia2022-10-021-1/+1
| | | | | | All patches automatically rebased. Signed-off-by: John Audia <therealgraysky@proton.me>
* realtek: use correct CAUSEF_DC macro in prom.cSander Vanheule2022-10-011-1/+1
| | | | | | | | The workaround for an already-enabled R4K timer used a non-existent macro CAUSE_DC. Fix compiling by using the actual macro CAUSEF_DC. Fixes: b7aab1958591 ("realtek: SMP handling of R4K timer interrupts") Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: SMP handling of R4K timer interruptsMarkus Stockhausen2022-10-011-3/+9
| | | | | | | | | | | | | | | | | | | Until now there has been no good explanation why we mess with the R4K timer on SMP. After extensive testing and looking at the SDK code it becomes clear what it is all about. When we disable the CEVT_R4K module (we will do with the new timer driver) the R4K timer hardware still fires interrupts on the secondary CPU. To get around this we have two options: - Disable IRQ 7 - Stop the counter completely This patch selects option two because this is the root of evil.. To be on the safe side we will do it only in case the CEVT_R4K module is disabled. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: fix SMP startupMarkus Stockhausen2022-10-011-2/+1
| | | | | | | | The scope of the SMP startup structure is wrong. It is created on the stack and not as a global variable. This can lead to startup failures. Fixes: 3f41360eb70c ("realtek: use upstream recommendation for CPU start") Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de
* realtek: Convert incorrect v5.10 patchesOlliver Schinagl2022-10-0127-1/+470
| | | | | | | | | | | | | | | | | OpenWRT's developer guide prefers having actual patches so they an be sent upstream more easily. However, in this case, Adding proper fields also allows for `git am` to properly function. Some of these patches are quite old, and lack much traceable history. This commit tries to rectify that, by digging in the history to find where and how it was first added. It is by no means perfect and also shows some patches that should have been long gone. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
* kernel: move kernel image cmdline hack to the octeon targetFelix Fietkau2022-09-301-14/+0
| | | | | | It is the only remaining user of this hack Signed-off-by: Felix Fietkau <nbd@nbd.name>
* realtek: rtl931x: fix missing CONFIG_COMMON_CLK_REALTEK config flagChristian Marangi2022-09-281-0/+1
| | | | | | | | | When the realtek clock driver was introduced, CONFIG_COMMON_CLK_REALTEK was not correctly disabled for other subtarget. Add the missing config flag to fix compilation error on buildbot. Fixes: 4850bd887c3a ("realtek: add RTL83XX clock driver") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* realtek: fix RTL839x egress tag for ports >= 32Jan Hoffmann2022-09-251-1/+1
| | | | | | | Don't overwrite AS_DPM and L2LEARNING flags when dest_port is >= 32. Fixes: 1773264a0c6d ("realtek: correct egress frame port verification") Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* kernel: bump 5.10 to 5.10.144John Audia2022-09-221-5/+5
| | | | | | All patches automatically rebased. Signed-off-by: John Audia <therealgraysky@proton.me>
* realtek: use upstream recommendation for secondary CPU startMarkus Stockhausen2022-09-182-26/+31
| | | | | | | | | | | Currently we fix interrupts/timers for the secondary CPU by patching vsmp_init_secondary(). Get a little bit more generic and use the upstream recommended way instead. Additionally avoid a check around register_cps_smp_ops() because it does that itself. See https://lkml.org/lkml/2022/9/12/522 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: avoid wrong interrupt routingMarkus Stockhausen2022-09-181-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interrupt controller depends on two control registers. GIMR enables or disables interrupts and IRRx routes these to MIPS CPU interrupts 2-7. Wiki currently states "A value of '0' (in IRRx) disconnects this input from the output line, independent of the line's setting in GIMR." Contrary to normal intuition this statement DOES NOT mean, that interrupts can be disabled by IRRx alone. The sad truth was discovered by enabling SMP for an Zyxel XGS1010 on the 930x target. It shows that driver and interrupts behave as follows: - Timer 0 interrupt 7 has active routing to CPU0 and no routing to CPU1 - Timer 1 interrupt 8 has no routing to CPU0 and active routing to CPU1 - Unmasking (enabling) interrupts writes 1 bits to all GIMR registers - Masking (disabling) interrupts writes 0 bits to both GIMR registers During operation we can encounter a situation like - GIMR bit for a interrupt/CPU combination is set to enabed (=1) - IRRx routing bits for a interrupt/CPU combination are set to disabed (=0) This setting already allows the hardware to fire interrupts to the target CPU/VPE if the other CPU/VPE is currently busy. Especially for CPU bound timer interrupts this is lethal. If timer interrupt 7 arrives at CPU1 and vice versa for interrupt 8 the restart trigger gets lost. The timer dies and a msleep() operation in the kernel will halt endlessly. Fix this by tracking the IRRx active routing setting in a new bitfield with 0="routing active" and 1="no routing". Enable interrupts in GIMR only for a interrupt & CPU if routing is active. Thus we have - GIMR = 0 / IRRx = 0 -> everything disabled - GIMR = 1 / IRRx > 0 -> active and normal routing - GIMR = 0 / IRRx > 0 -> masked (disabled) with normal routing - GIMR = 1 / IRRx = 0 -> no longer possible Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: use Device prefix for common recipesSander Vanheule2022-09-183-13/+13
| | | | | | | | | | | The Build prefix is used for image build commands, while the Device prefix should be used for base recipes for devices. Apply the same naming convention here. While touching the file, also fix the mixed indentation. Suggested-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: move Netgear recipe to subtarget MakefileOlliver Schinagl2022-09-172-10/+10
| | | | | | | | | | There seems to be no reason to have the Netgear switches as part of the main Makefile. Move it to its subtarget-specific Makefile since it is only applicable there. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> [update commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: move hpe_1920 recipe to common.mkSander Vanheule2022-09-173-14/+14
| | | | | | | | | Currently supported HPE 1920 devices all have an RTL838x SoC, but there are larger switches with RTL839x SoCs, although currently not supported. Move the build recipe to common.mk so the larger devices can also make use of the recipe, while moving it out of the main Makefile. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: merge duplicated DGS-1210 recipesSander Vanheule2022-09-173-37/+29
| | | | | | | | | | | | The D-Link DGS-1210 device series currently has supported devices with both RTL838x and RTL839x SoCs. An image build recipe has been defined in both subtarget makefiles, but these are mostly identical, save for the SOC variable. Move the SOC variable from the DGS-1210 build recipes to the applicable devices, and put the remaining duplicate code in a shared Makefile. Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add support for DGS-1210-52Markus Stockhausen2022-09-173-0/+260
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware specification ---------------------- * RTL8393M SoC, 1 MIPS 34Kc core @ 700MHz * 128MB DRAM * 32MB NOR Flash * 48 x 10/100/1000BASE-T ports - 6 x External PHY with 8 ports (RTL8218D) * 4 x Gigabit RJ45/SFP Combo ports - External PHY with 4 SFP ports (RTL8214FC) * Power LED * Reset button on front panel * UART (115200 8N1) via unpopulated standard 0.1" pin header marked J14 The gpio-restart node is not required but it does reset the switch. TODO: The 4 combo ports attached to the RTL8214FC are not detect properly. Linux kernel reports 49 and 50 as "External RTL8393 SERDES" and 51 and 52 as "RTL8218B (external)". Those ports only work if u-boot initialize it (for example, loading initramfs image using one of those ports). A patch to PHY detection is needed for full support. The firmware recovery using U-Boot is broken for all DGS-1210 tested devices as pressing RESET does not trigger it (only if pressed from a running stock image) UART pinout ----------- [o]ooo|J14 | ||`------ GND | |`------- RX | `-------- TX `---------- Vcc (3V3) Installation using OEM upgrade ------------------------------ 1. Make sure you are running OEM firmware in image2 slot (logged as admin): - > config firmware image_id 2 boot_up - > reboot 2. Install squashfs-factory_image1.bin to image1 using (logged as admin): - > download firmware_fromTFTP <tftpserver> factory_image1.bin - > config firmware image_id 1 boot_up - > reboot Installation using serial interface ----------------------------------- 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. Press CTRL+C keys to get into real U-Boot prompt 3. Init network with `rtk network on` command 4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl839x-d-link_dgs-1210-52-initramfs-kernel.bin` command 5. Boot the image with `bootm` command Once booted the initramfs, install the squashfs-sysupgrade.bin as a normal OpenWrt system. Dual-boot with stock firmware using writable u-boot-env ------------------------------------------------------- From stock to OpenWrt / boot image 1 (CLI as admin): - > config firmware image_id 1 boot_up - > reboot From OpenWrt to stock / boot image 2: (shell as root) - # fw_setenv bootcmd 'run addargs ; bootm 0xb4e80000' - # fw_setenv image '/dev/mtdblock7' - # reboot Debrick using serial interface ------------------------------ 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should detect the switch 3. Flash the firmware. Back to stock firmware using dual-boot -------------------------------------- If you have serial interface, you can change u-boot env vars interrupting the boot process. If not but you are running OpenWrt, you can dual-boot (as mentioned eariler) and skip to step 4: 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. Press CTRL+C keys to get into real U-Boot prompt 3. Boot the image 2: - set image /dev/mtdblock7; run addargs; bootm 0xb4e80000 4. Once booted, log as admin and change the boot image to 2 - > config firmware image_id 2 boot_up - > reboot 5. After the boot, flash image1 with the vendor image Back to stock firmware using DNA -------------------------------- 1. From an OpenWrt: - # fw_setenv bootstop on - # reboot 2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should detect the switch 3. Flash the firmware. It has been developed and tested on device with F3 revision. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
* realtek: align DT macros in RTL839X with RTL838XMarkus Stockhausen2022-09-171-0/+7
| | | | | | Add a missing definition to the RTL839X DT. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: D-Link make common DT include genericMarkus Stockhausen2022-09-176-7/+10
| | | | | | | | | | | | | | | | | | | | The D-Link DGS device tree was reorganized to better reflect the common DT parts. The common include is named SOC specific (838X) and it seemed like a good choice to add another common include in the future for the RTL839X devices. From the current point of view this option is not really needed. 1. The common part only includes data that matches RTL839X devices too. 2. The Panasonic DT structure avoids including the basic DTSI inside the common DTSI. Taking simplicity of the Panasonic include logic and in perparation to provide DGS-1210-52 support it makes sense to harmonize this. - rename common include to reflect its content - move the link to the root DTSI directly to the device specific DTS Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
* realtek: rtl838x: Fix ethernet polling timeout on probeOlliver Schinagl2022-09-141-1/+2
| | | | | | | | | | Due to an oversight we accidentally inverted the timeout check. This patch corrects this. Fixes: 9cec4a0ea45b ("realtek: Use built-in functionality for timeout loop") Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> [ wrap poll_timeout line to 80 char ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* realtek: Use built-in functionality for timeout loopOlliver Schinagl2022-09-141-12/+7
| | | | | | | | | | In commit 81e3017609be ("realtek: clean up rtl838x MDIO busy wait loop") a hand-crafted loop was created, that nearly exactly replicate the iopoll's `read_poll_timeout` functionality. Use that instead. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
* realtek: add support for TP-Link SG2210PAlexandru Gagniuc2022-09-136-2/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the TP-Link SG2210P switch. This is an RTL8380 based switch with eight RJ-45 ports with 802.3af PoE, and two SFP ports. This device shares the same board with the SG2008P and SG2008. To model this, declare all the capabilities in the sg2xxx dtsi, and disable unpopulated on the lower end models. Specifications: --------------- - SoC: Realtek RTL8380M - Flash: 32 MiB SPI flash (Vendor varies) - RAM: 256 MiB (Vendor varies) - Ethernet: 8x 10/100/1000 Mbps with PoE (all ports) 2x SFP ports - Buttons: 1x "Reset" button on front panel - Power: 53.5V DC barrel jack - UART: 1x serial header, unpopulated - PoE: 2x TI TPS23861 I2C PoE controller Works: ------ - (8) RJ-45 ethernet ports - (2) SFP ports (with caveats) - Switch functions - System LED Not yet enabled: ---------------- - Power-over-Ethernet (driver works, but doesn't enable "auto" mode) - PoE LEDs Enabling SFP ports: ------------------- The SFP port control lines are hardwired, except for tx-disable. These lines are controller by the RTL8231 in shift register mode. There is no driver support for this yet. However, to enable the lasers on SFP1 and SFP2 respectively: echo 0x0510ff00 > /sys/kernel/debug/rtl838x/led/led_p_en_ctrl echo 0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.26 echo 0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.24 Install via serial console/tftp: -------------------------------- The footprints R27 (0201) and R28 (0402) are not populated. To enable serial console, 50 ohm resistors should be soldered -- any value from 0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge. The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at 38400 baud. There is no known way to exit out of this shell, and no way to do anything useful. Ideally, one would trick the bootloader into flashing the sysupgrade image first. However, if the image exceeds 6MiB in size, it will not work. The sysupgrade image can also be flashed. To install OpenWrt: Prepare a tftp server with: 1. server address: 192.168.0.146 2. the image as: "uImage.img" Power on device, and stop boot by pressing any key. Once the shell is active: 1. Ground out the CLK (pin 16) of the ROM (U7) 2. Select option "3. Start" 3. Bootloader notes that "The kernel has been damaged!" 4. Release CLK as sson as bootloader thinks image is corrupted. 5. Bootloader enters automatic recovery -- details printed on console 6. Watch as the bootloader flashes and boots OpenWrt. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [OpenWrt capitalisation in commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: rtl8380-tl-sg2xxx: use a single "firmware" partitionAlexandru Gagniuc2022-09-131-25/+4
| | | | | | | | | The "firmware" partition was assembled from two contiguous partitions. This complexity is unnecessary. Instead of using mtd-concat over "sys" and "usrimg1", simply declare the "firmware" partition to cover the flash space instead. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: tl-sg2xxx: read MAC address from nvmem-cellsAlexandru Gagniuc2022-09-133-1/+23
| | | | | | | | | | | | | The TP-Link RTL83xx based switches have their MAC address programmed in the "para" partition. While in theory, the format of this partition is dynamic, in practice, the MAC address appears to be located at a consistent address. Thus, use nvmem-cells to read this MAC address. The main MAC is required for deriving the MAC address of the switch ports. Instead of reading it via mtd_get_mac_binary(), alias the ethernet0 node as the label-mac-device, and use get_mac_label(). Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: rtl838x: label switch port dts nodesAlexandru Gagniuc2022-09-131-2/+2
| | | | | | | | Although PHY nodes are labeled, the port nodes were not. Labeling of ports is useful for 'status = "disabled"' ports, which is supported since commit 9a7f17e11f5d ("realtek: ignore disabled switch ports") Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* realtek: split TP-Link SG2000 series devicetreeAlexandru Gagniuc2022-09-132-177/+182
| | | | | | | | | | | | The TP-Link TL-SG2008, TL-SG2008P, and TL-SG2210P use the same board. The main difference is that some footprints are not populated in the lower-end models. To model this with minimal duplication, move the devicetree to a common dtsi, leaving out just the board name. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [remove port relabelling from commit message, already merged with commit 18a2b29aa1c9 ("realtek: tl-sg2008p: fix labeling of lan ports")] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add support for TP-Link SG2452P v4 aka T1600G-52PS v4Andreas Böhler2022-09-104-1/+428
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an RTL8393-based switch with 802.3af on all 48 ports. Specifications: --------------- * SoC: Realtek RTL8393M * Flash: 32 MiB SPI flash * RAM: 256 MiB * Ethernet: 48x 10/100/1000 Mbps with PoE+ * Buttons: 1x "Reset" button, 1x "Speed" button * UART: 1x serial header, unpopulated * PoE: 12x TI TPS23861 I2C PoE controller, 384W PoE budget * SFP: 4 SFP ports Works: ------ - (48) RJ-45 ethernet ports - Switch functions - Buttons - All LEDs on front panel except port LEDs - Fan monitoring and basic control Not yet enabled: ---------------- - PoE - ICs are not in AUTO mode, so the kernel driver is not usable - Port LEDs - SFP cages Install via web interface: ------------------------- Not supported at this time. Install via serial console/tftp: -------------------------------- The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at 38400 baud. There is no known way to exit out of this shell, and no way to do anything useful. Ideally, one would trick the bootloader into flashing the sysupgrade image first. However, if the image exceeds 6MiB in size, it will not work. To install OpenWRT: Prepare a tftp server with: 1. server address: 192.168.0.146 2. the image as: "uImage.img" Power on device, and stop boot by pressing any key. Once the shell is active: 1. Ground out the CLK (pin 16) of the ROM (U6) 2. Select option "3. Start" 3. Bootloader notes that "The kernel has been damaged!" 4. Release CLK as soon as bootloader thinks image is corrupted. 5. Bootloader enters automatic recovery -- details printed on console 6. Watch as the bootloader flashes and boots OpenWRT. Blind install via tftp: ----------------------- This method works when it's not feasible to install a serial header. Prepare a tftp server with: 1. server address: 192.168.0.146 2. the image as: "uImage.img" 3. Watch network traffic (tcpdump or wireshark works) 4. Power on the device. 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6) 6. When 192.168.0.30 makes tftp requests, release pin 16 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT Signed-off-by: Andreas Böhler <dev@aboehler.at>
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