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* realtek: fix locking bug in rtl838x_hw_receive()Birger Koblitz2022-02-181-3/+4
| | | | | | | | | | | | | | A Locking bug in the packet receive path was introduced with PR #4973. The following patch prevents the driver from locking after a few minutes with an endless flow of [ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8 [ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc [ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc [ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
* realtek: add RTL8231 chip detectionSander Vanheule2022-02-171-1/+14
| | | | | | | | | | | | | | | | | | | | | | When initialising the driver, check if the RTL8231 chip is actually present at the specified address. If the READY_CODE value does not match the expected value, return -ENXIO to fail probing. This should help users to figure out which address an RTL8231 is configured to use, if measuring pull-up/-down resistors is not an option. On an unsuccesful probe, the driver will log: [ 0.795364] Probing RTL8231 GPIOs [ 0.798978] rtl8231_init called, MDIO bus ID: 30 [ 0.804194] rtl8231-gpio rtl8231-gpio: no device found at bus address 30 When a device is found, only the first two lines will be logged: [ 0.453698] Probing RTL8231 GPIOs [ 0.457312] rtl8231_init called, MDIO bus ID: 31 Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: always require SMI bus ID for RTL8231Sander Vanheule2022-02-171-17/+16
| | | | | | | | | | | | | | | The SMI bus ID for RTL8231 currently defaults to 0, and can be overridden from the devicetree. However, there is no value check on the DT-provided value, aside from masking which would only cause value wrap-around. Change the driver to always require the "indirect-access-bus-id" property, as there is no real reason to use 0 as default, and perform a sanity check on the value when probing. This allows the other parts of the driver to be simplified a bit. Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: use automatic GPIO numbering for RTL8231Sander Vanheule2022-02-171-1/+1
| | | | | | | | | Set the gpio_chip.base to -1 to use automatic GPIO line indexing. Setting base to 0 or a positive number is deprecated and should not be used. Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: fix RTL8231 gpio countSander Vanheule2022-02-171-1/+1
| | | | | | | | | | The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the actual line count. Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: rtl83xx-phy: abstract and document PHY featuresDaniel Golle2022-02-171-114/+135
| | | | | | | | | | | | | Replace magic values with more self-descriptive code now that I start to understand more about the design of the PHY (and MDIO controller). Remove one line before reading RTL8214FC internal PHY id which turned out to be a no-op and can hence safely be removed (confirmed by INAGAKI Hiroshi[1]) [1]: https://github.com/openwrt/openwrt/commit/df8e6be59a1fbce3f8c6878fe7440a129b1245d6#r66890713 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: fix locking issuesBirger Koblitz2022-02-172-26/+22
| | | | | | | Fixe a coupld of locking issues found by applying lock debugging to the code. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: switch to use generic MDIO accessor functionsDaniel Golle2022-02-175-473/+398
| | | | | | | | Instead of directly calling SoC-specific functions in order to access (paged) MII registers or MMD registers, create infrastructure to allow using the generic phy_*, phy_*_paged and phy_*_mmd functions. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: implement Clause-45 MDIO write on rtl931xDaniel Golle2022-02-172-26/+65
| | | | | | | | | * Add missing Clause-45 write support for rtl931x * Switch to use helper functions in all Clause-45 access functions to make the code more readable. * More meaningful/unified debugging output (dynamic kprintf) Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: add support for port led configuration on RTL93XXBirger Koblitz2022-02-176-8/+175
| | | | | | | | | Using the led-set attribute of a port in the dts we allow configuration of the port leds. Each led-set is being defined in the led-set configuration of the .dts, giving a specific configuration to steer the port LEDs via a serial connection. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for the RTL8221B PHYBirger Koblitz2022-02-172-0/+18
| | | | | | | | | The RTL8221B PHY is a newer version of the RTL8226, also supporting 2.5GBit Ethernet. It is found with RTL931X devices such as the EdgeCore ECS4125-10P Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210Birger Koblitz2022-02-172-14/+101
| | | | | | | | | | Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the Zyxel XGS1210 require special polling configuration settings in the RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them. Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits in the poll mask. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix link status detection on RTL9302 for SFP modulesBirger Koblitz2022-02-172-3/+23
| | | | | | | For SFP slots on the RTL9302, the link status is not correctly detected. Use the link media status instead. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add RTL931X sub-targetBirger Koblitz2022-02-171-0/+25
| | | | | | | | We add the RTL931X sub-target with kernel configuration for a dual core MIPS InterAptive CPU. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add HW support for RTL931X for PIE, L2 and STP agingBirger Koblitz2022-02-172-52/+1188
| | | | | | | | We add HW support routines for the RTL931X SoC family for handling the Packet Inspection Engine, L2 table handling and STP aging. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Store and Restore MC memberships for port enable/disableBirger Koblitz2022-02-172-55/+86
| | | | | | | | | We need to store and restore MC memberships in HW when a port joins or leaves a bridge as well as when it is enabled or disabled, as these properties should not change in these situations. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Copy all BPDUs to the kernelBirger Koblitz2022-02-174-8/+140
| | | | | | | | In order to receive STP information at the kernel level, we make sure that all Bridge Protocol Data Units are copied to the CPU-Port. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add L2 aging configuration functions for all SoC familiesBirger Koblitz2022-02-176-19/+58
| | | | | | | | Instead of a generic L2 aging configuration function with complex logic, we implement an individual function for all SoC types. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realted: Add DSA bridge offload configurationBirger Koblitz2022-02-174-1/+139
| | | | | | | | Add functionality to enable or disable L2 learning offload and port flooding for RTL83XX. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add Link Aggregation (aka trunking) supportBirger Koblitz2022-02-178-15/+369
| | | | | | | | | This adds LAG support for all 4 SoC families, including support ofr the use of different distribution algorithm for the load- balancing between individual links. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filteringBirger Koblitz2022-02-176-28/+189
| | | | | | | | Use setting functions instead of register numbers in order to clean up the code. Also use enums to define inner/outer VLAN types and the filter type. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SDS configuration routines for the RTL93XX platformsBirger Koblitz2022-02-174-44/+2144
| | | | | | | | Adds configuration routines for the internal SerDes of the RTL930X and RTL931X. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve MAC config handling for all SoCsBirger Koblitz2022-02-173-34/+205
| | | | | | | | | Adds a rtl931x_phylink_mac_config for the RTL931X and improve the handling of the RTL930X phylink configuration. Add separate handling of the RTL839x since some configurations are different from the RTL838X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for detecting RTL9303 SoCsBirger Koblitz2022-02-171-0/+4
| | | | | | | Adds support for detecting RTL9303 SoCs as found e.g. in the Ubiquiti USW switch. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Allow PHY-IDs to differ from Port numbersBirger Koblitz2022-02-171-9/+34
| | | | | | | | | We were using the PHY-ids (the reg entries in the PHY sections of the .dts) as the port numbers. Now scan the ports section in the .dts, and use the actual port numbers, following the phy-handle to the PHY properties. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Use SerDes Information from .dts for phylink configBirger Koblitz2022-02-172-5/+27
| | | | | | | | When a port is brought up, read the SDS-id via the phy_device for a given port and use this to configure the SDS when it is brought up. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve IRQ request in Ethernet driverBirger Koblitz2022-02-171-5/+4
| | | | | | | Improves the IRQ request code by using platform_get_irq() which provides better error handling. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Replace the RTL9300 generic timer with a CEVT timerBirger Koblitz2022-02-172-196/+212
| | | | | | | | | | | | | | The RTL9300 has a broken R4K MIPS timer interrupt, however, the R4K clocksource works. We replace the RTL9300 timer with a Clock Event Timer (CEVT), which is VSMP aware and can be instantiated as part of brining a VSMTP cpu up instead of the R4K CEVT source. For this we place the RTL9300 CEVT timer in arch/mips/kernel together with other MIPS CEVT timers, initialize the SoC IRQs from a modified smp-mt.c and instantiate each timer as part of the MIPS time setup in arch/mips/include/asm/time.h instead of the R4K CEVT, similarly as is done by other MIPS CEVT timers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X Ethernet driverBirger Koblitz2022-02-171-21/+167
| | | | | | | | | | Various fixes to enable Ethernet on the RTL931X: - Network start and stop sequence for RTL931X HW - MDIO access on RTL931X SoC - Chip initialization - SerDes setup Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix Ethernet driver IRQ service routine for SMPBirger Koblitz2022-02-171-5/+0
| | | | | | | Do not lock the register structure in IRQ context. It is not necessary and leads to lockups under SMP load. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: fix RTL839X receive tag decodingBirger Koblitz2022-02-171-4/+5
| | | | | | Correct offset in RX tag structure. Correct offload decision flagging. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SerDes access functions for RTL931XBirger Koblitz2022-02-172-0/+52
| | | | | | Adds RTL931X SerDes access functions as needed by the Ethernet driver. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X-specific Ethernet driver functionsBirger Koblitz2022-02-173-30/+47
| | | | | | | Fix the update counter of the RX ring, add SDS access functions for RTL931X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: rename rtl838x_reg structureBirger Koblitz2022-02-172-6/+6
| | | | | | | | Rename the SoC-specific rtl838x_reg structure in the Ethernet driver to avoid confusion with the structure of the same name in the DSA driver. New name is: rtl838x_eth_reg Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL839x TX CPU-TagBirger Koblitz2022-02-171-2/+2
| | | | | | | | | | Setting bits 20 and 23 in a u16 is obviously wrong. According to https://www.svanheule.net/realtek/cypress/cputag cpu_tag[2] starts at bit 48 in the cpu-tag structure, so bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in cpu_tag[2]. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Increase zone size for Ethernet driver DMABirger Koblitz2022-02-171-2/+2
| | | | | | | | | | Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger contiguous memory allocation for the DMA of the Ethernet driver. Increase the number of entries in the RX ring to 300 making use of the larger DMA region now possible for receiveing packets. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Enable Multithreading support in prom.cBirger Koblitz2022-02-171-0/+20
| | | | | | Adds Multithreading support functions in prom.c. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Change Platform defines to depend on CONFIG_RTL83XXBirger Koblitz2022-02-171-2/+2
| | | | | | | In order for the Platform includes to be available on all sub-targets, make them dependent on CONFIG_RTL83XX. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Create 4 different Realtek PlatformsBirger Koblitz2022-02-171-1/+1
| | | | | | | | Creates RTL83XX as a basic kernel config parameter for the RTL838X, RTL839x, RTL930X and RTL931X platforms with respective configurations for the SoCs, which are introduced in addition. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for RTL9300/RTL9310 I2C multiplexingBirger Koblitz2022-02-172-37/+330
| | | | | | | | | | | | The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C masters, each with a fixed SCL pin, that cannot be changed. Each of these masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA. This multiplexer directly controls the two masters and their shared IO configuration registers to allow multiplexing between any of these busses. The two masters cannot be used in parallel as the multiplex is protected by a standard multiplex lock. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for RTL9300/RTL9310 I2C controllerBirger Koblitz2022-02-172-0/+550
| | | | | | | | | | This adds support for the RTL9300 and RTL9310 I2C controller. The controller implements the SMBus protocol for SMBus transfers over an I2C bus. The driver supports selecting one of the 2 possible SCL pins and any of the 8 possible SDA pins. Bus speeds of 100kHz (standard speed) and 400kHz (high speed I2C) are supported. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: remove legacy GPIO driver supportBirger Koblitz2022-02-171-474/+0
| | | | | | | This patch removes support for the legacy GPIO driver, since now the gpio-otto driver can be used on all platforms Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Remove _machine_restart and _machine_haltSander Vanheule2021-11-241-85/+0
| | | | | | | | | | | | | | By dropping _machine_restart, users can provide more reliable or device-specific restart modes. _machine_halt was already removed in commit f4b687d1f053 ("realtek: use kernel defined halt"), but quietly reintroduced in commit 8faffa00cb6b ("realtek: add support for the RTL9300 timer"). Let's remove it again. Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Segers <foss@volatilesystems.org> Tested-by: Paul Fertser <fercerpav@gmail.com> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: reset both ethernet NIC and queuesSander Vanheule2021-11-241-4/+7
| | | | | | | | | | | | | | | Recent versions of Realtek's SDK reset both the ethernet NIC and queues (SW_NIC_RST and SW_Q_RST bits) when initialising the hardware. Furthermore, when issuing a CPU reset on the Zyxel GS1900-8 (not supported by any current driver), the networking part of the SoC is not reset. This leads to unresponsive network after the restart. By resetting both the ethernet NIC and queues, networking always comes up reliably. Suggested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: re-enable IPv6 routingBjørn Mork2021-10-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Commit 03e1d93e0779 ("realtek: add driver support for routing offload") added routing offload for IPv4, but broke IPv6 routing completely. The routing table is empty and cannot be updated: root@gs1900-10hp:~# ip -6 route root@gs1900-10hp:~# ip -6 route add unreachable default RTNETLINK answers: Invalid argument As a side effect, this breaks opkg on IPv4 only systems too, since uclient-fetch fails when there are no IPv6 routes: root@gs1900-10hp:~# uclient-fetch http://192.168.99.1 Downloading 'http://192.168.99.1' Failed to send request: Operation not permitted Fix by returning NOTIFY_DONE when offloading is unsupported, falling back to default behaviour. Fixes: 03e1d93e0779 ("realtek: add driver support for routing offload") Signed-off-by: Bjørn Mork <bjorn@mork.no>
* realtek: add legacy realtek GPIO driver for rtl9300 supportBirger Koblitz2021-10-092-0/+481
| | | | | | | The otto GPIO driver does not work with rtl9300 SoCs. Add the legacy driver again and use that by default in the 9300 .dtsi Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix bug when accessing external PHYs on SoCs older than Revision CBirger Koblitz2021-10-091-3/+22
| | | | | | | | | | RTL8393 SoCs older than Revision C hang on accesses to PHYs with PHY address larger or equal to the CPU-port (52). This will make scanning the MDIO bus hang forever. Since the RTL8390 platform does not support more than 52 PHYs, return -EIO for phy addresses >= 52. Note that the RTL8390 family of SoCs has a fixed mapping between port number and PHY-address. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: cleanup PHY driverBirger Koblitz2021-10-091-8/+6
| | | | | | Removes unnecessary output from the RTL PHY drivers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add debugfs support for RTL9300Birger Koblitz2021-10-092-1/+130
| | | | | | Adds support for debugfs on RTL9300, in particular the drop counters. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SoC-specific routing offload implementationBirger Koblitz2021-10-094-165/+938
| | | | | | | | Adds SoC specific routing offload implementations for RTL8380/90 and RTL9300. RTL83xx supports merely nexthop routing, RTL9300 full host and prefix routes. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-27 09:57:34 +0000