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* realted: Add DSA bridge offload configurationBirger Koblitz2022-02-174-1/+139
| | | | | | | | Add functionality to enable or disable L2 learning offload and port flooding for RTL83XX. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add Link Aggregation (aka trunking) supportBirger Koblitz2022-02-178-15/+369
| | | | | | | | | This adds LAG support for all 4 SoC families, including support ofr the use of different distribution algorithm for the load- balancing between individual links. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filteringBirger Koblitz2022-02-176-28/+189
| | | | | | | | Use setting functions instead of register numbers in order to clean up the code. Also use enums to define inner/outer VLAN types and the filter type. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SDS configuration routines for the RTL93XX platformsBirger Koblitz2022-02-174-44/+2144
| | | | | | | | Adds configuration routines for the internal SerDes of the RTL930X and RTL931X. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve MAC config handling for all SoCsBirger Koblitz2022-02-173-34/+205
| | | | | | | | | Adds a rtl931x_phylink_mac_config for the RTL931X and improve the handling of the RTL930X phylink configuration. Add separate handling of the RTL839x since some configurations are different from the RTL838X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for detecting RTL9303 SoCsBirger Koblitz2022-02-171-0/+4
| | | | | | | Adds support for detecting RTL9303 SoCs as found e.g. in the Ubiquiti USW switch. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Allow PHY-IDs to differ from Port numbersBirger Koblitz2022-02-171-9/+34
| | | | | | | | | We were using the PHY-ids (the reg entries in the PHY sections of the .dts) as the port numbers. Now scan the ports section in the .dts, and use the actual port numbers, following the phy-handle to the PHY properties. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Use SerDes Information from .dts for phylink configBirger Koblitz2022-02-172-5/+27
| | | | | | | | When a port is brought up, read the SDS-id via the phy_device for a given port and use this to configure the SDS when it is brought up. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve IRQ request in Ethernet driverBirger Koblitz2022-02-171-5/+4
| | | | | | | Improves the IRQ request code by using platform_get_irq() which provides better error handling. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Replace the RTL9300 generic timer with a CEVT timerBirger Koblitz2022-02-172-196/+212
| | | | | | | | | | | | | | The RTL9300 has a broken R4K MIPS timer interrupt, however, the R4K clocksource works. We replace the RTL9300 timer with a Clock Event Timer (CEVT), which is VSMP aware and can be instantiated as part of brining a VSMTP cpu up instead of the R4K CEVT source. For this we place the RTL9300 CEVT timer in arch/mips/kernel together with other MIPS CEVT timers, initialize the SoC IRQs from a modified smp-mt.c and instantiate each timer as part of the MIPS time setup in arch/mips/include/asm/time.h instead of the R4K CEVT, similarly as is done by other MIPS CEVT timers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X Ethernet driverBirger Koblitz2022-02-171-21/+167
| | | | | | | | | | Various fixes to enable Ethernet on the RTL931X: - Network start and stop sequence for RTL931X HW - MDIO access on RTL931X SoC - Chip initialization - SerDes setup Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix Ethernet driver IRQ service routine for SMPBirger Koblitz2022-02-171-5/+0
| | | | | | | Do not lock the register structure in IRQ context. It is not necessary and leads to lockups under SMP load. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: fix RTL839X receive tag decodingBirger Koblitz2022-02-171-4/+5
| | | | | | Correct offset in RX tag structure. Correct offload decision flagging. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SerDes access functions for RTL931XBirger Koblitz2022-02-172-0/+52
| | | | | | Adds RTL931X SerDes access functions as needed by the Ethernet driver. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL931X-specific Ethernet driver functionsBirger Koblitz2022-02-173-30/+47
| | | | | | | Fix the update counter of the RX ring, add SDS access functions for RTL931X. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: rename rtl838x_reg structureBirger Koblitz2022-02-172-6/+6
| | | | | | | | Rename the SoC-specific rtl838x_reg structure in the Ethernet driver to avoid confusion with the structure of the same name in the DSA driver. New name is: rtl838x_eth_reg Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix RTL839x TX CPU-TagBirger Koblitz2022-02-171-2/+2
| | | | | | | | | | Setting bits 20 and 23 in a u16 is obviously wrong. According to https://www.svanheule.net/realtek/cypress/cputag cpu_tag[2] starts at bit 48 in the cpu-tag structure, so bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in cpu_tag[2]. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Increase zone size for Ethernet driver DMABirger Koblitz2022-02-171-2/+2
| | | | | | | | | | Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger contiguous memory allocation for the DMA of the Ethernet driver. Increase the number of entries in the RX ring to 300 making use of the larger DMA region now possible for receiveing packets. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Enable Multithreading support in prom.cBirger Koblitz2022-02-171-0/+20
| | | | | | Adds Multithreading support functions in prom.c. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Change Platform defines to depend on CONFIG_RTL83XXBirger Koblitz2022-02-171-2/+2
| | | | | | | In order for the Platform includes to be available on all sub-targets, make them dependent on CONFIG_RTL83XX. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Create 4 different Realtek PlatformsBirger Koblitz2022-02-171-1/+1
| | | | | | | | Creates RTL83XX as a basic kernel config parameter for the RTL838X, RTL839x, RTL930X and RTL931X platforms with respective configurations for the SoCs, which are introduced in addition. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for RTL9300/RTL9310 I2C multiplexingBirger Koblitz2022-02-172-37/+330
| | | | | | | | | | | | The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C masters, each with a fixed SCL pin, that cannot be changed. Each of these masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA. This multiplexer directly controls the two masters and their shared IO configuration registers to allow multiplexing between any of these busses. The two masters cannot be used in parallel as the multiplex is protected by a standard multiplex lock. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add support for RTL9300/RTL9310 I2C controllerBirger Koblitz2022-02-172-0/+550
| | | | | | | | | | This adds support for the RTL9300 and RTL9310 I2C controller. The controller implements the SMBus protocol for SMBus transfers over an I2C bus. The driver supports selecting one of the 2 possible SCL pins and any of the 8 possible SDA pins. Bus speeds of 100kHz (standard speed) and 400kHz (high speed I2C) are supported. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: remove legacy GPIO driver supportBirger Koblitz2022-02-171-474/+0
| | | | | | | This patch removes support for the legacy GPIO driver, since now the gpio-otto driver can be used on all platforms Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Remove _machine_restart and _machine_haltSander Vanheule2021-11-241-85/+0
| | | | | | | | | | | | | | By dropping _machine_restart, users can provide more reliable or device-specific restart modes. _machine_halt was already removed in commit f4b687d1f053 ("realtek: use kernel defined halt"), but quietly reintroduced in commit 8faffa00cb6b ("realtek: add support for the RTL9300 timer"). Let's remove it again. Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Segers <foss@volatilesystems.org> Tested-by: Paul Fertser <fercerpav@gmail.com> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: reset both ethernet NIC and queuesSander Vanheule2021-11-241-4/+7
| | | | | | | | | | | | | | | Recent versions of Realtek's SDK reset both the ethernet NIC and queues (SW_NIC_RST and SW_Q_RST bits) when initialising the hardware. Furthermore, when issuing a CPU reset on the Zyxel GS1900-8 (not supported by any current driver), the networking part of the SoC is not reset. This leads to unresponsive network after the restart. By resetting both the ethernet NIC and queues, networking always comes up reliably. Suggested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Sander Vanheule <sander@svanheule.net> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
* realtek: re-enable IPv6 routingBjørn Mork2021-10-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Commit 03e1d93e0779 ("realtek: add driver support for routing offload") added routing offload for IPv4, but broke IPv6 routing completely. The routing table is empty and cannot be updated: root@gs1900-10hp:~# ip -6 route root@gs1900-10hp:~# ip -6 route add unreachable default RTNETLINK answers: Invalid argument As a side effect, this breaks opkg on IPv4 only systems too, since uclient-fetch fails when there are no IPv6 routes: root@gs1900-10hp:~# uclient-fetch http://192.168.99.1 Downloading 'http://192.168.99.1' Failed to send request: Operation not permitted Fix by returning NOTIFY_DONE when offloading is unsupported, falling back to default behaviour. Fixes: 03e1d93e0779 ("realtek: add driver support for routing offload") Signed-off-by: Bjørn Mork <bjorn@mork.no>
* realtek: add legacy realtek GPIO driver for rtl9300 supportBirger Koblitz2021-10-092-0/+481
| | | | | | | The otto GPIO driver does not work with rtl9300 SoCs. Add the legacy driver again and use that by default in the 9300 .dtsi Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix bug when accessing external PHYs on SoCs older than Revision CBirger Koblitz2021-10-091-3/+22
| | | | | | | | | | RTL8393 SoCs older than Revision C hang on accesses to PHYs with PHY address larger or equal to the CPU-port (52). This will make scanning the MDIO bus hang forever. Since the RTL8390 platform does not support more than 52 PHYs, return -EIO for phy addresses >= 52. Note that the RTL8390 family of SoCs has a fixed mapping between port number and PHY-address. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: cleanup PHY driverBirger Koblitz2021-10-091-8/+6
| | | | | | Removes unnecessary output from the RTL PHY drivers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add debugfs support for RTL9300Birger Koblitz2021-10-092-1/+130
| | | | | | Adds support for debugfs on RTL9300, in particular the drop counters. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SoC-specific routing offload implementationBirger Koblitz2021-10-094-165/+938
| | | | | | | | Adds SoC specific routing offload implementations for RTL8380/90 and RTL9300. RTL83xx supports merely nexthop routing, RTL9300 full host and prefix routes. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: add driver support for routing offloadBirger Koblitz2021-10-092-20/+946
| | | | | | | | Add generic support for listening to FIB and Event notifier updates and use this information to hook into the L3 hardware capabilities of the RTL SoCs. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve MDIO bus probing for RTL9300Birger Koblitz2021-10-091-21/+11
| | | | | | | Improve handling of multi-gig ports on the RTL9300 when probing the MDIO bus. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Fix bug in VLAN ingress and egress filteringBirger Koblitz2021-10-091-4/+4
| | | | | | | | | | | The ingress filter registers use 2 bits for each port to define the filtering state, whereas the egress filter uses 1 bit. So for for the ingress filter the register offset for a given port is: (port >> 4) << 4: since there are 16 entries in a register of 32 bits and for the egress filter: (port >> 5) << 4: since there are 32 entries in a register of 32 bits Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Configure initial L2 learning setupBirger Koblitz2021-10-095-1/+63
| | | | | | | | Configure a sane L2 learning configuration upon DSA driver load so that the switch can start learning L2 addresses. Also configure the correct flood masks for broadcast and unknown unicast traffice. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add phylink configuration routines for RTL93xxBirger Koblitz2021-10-092-20/+241
| | | | | | | | This adds RTL93xx-specific MAC configuration routines that allow also configuration of 10GBit links for phylink. There is support for the Realtek-specific HISGMI protocol. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Packet Inspection Engine support for RTL930x SoCsBirger Koblitz2021-10-091-0/+678
| | | | | | Adds the RTL930x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Packet Inspection Engine support for RTL839x SoCsBirger Koblitz2021-10-091-0/+875
| | | | | | Adds the RTL839x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Packet Inspection Engine support for RTL838x SoCsBirger Koblitz2021-10-091-0/+1007
| | | | | | Adds the RTL838x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add driver support for TC offloadingBirger Koblitz2021-10-098-3/+730
| | | | | | | | This adds support for offloading TC flower by using the Packet Inspection Engine of the RTL-SoCs. Basic infrastructure support is provide with callbacks to the tc subsystem and support for HW packet counters. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add port to smi-bus address mappingBirger Koblitz2021-10-091-32/+69
| | | | | | | | All RTL SoCs addresss PHYs via their port number, which is mapped to an SMI address. Add support for configuring this mapping via the .dts on all SoCs apart from the 839x, where the mapping to the 64 ports is fixed. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Increase maximum RX ring buffer lengthBirger Koblitz2021-10-091-4/+5
| | | | | | | Increase the maximum ring buffer length in order to improve performance on RTL839x devices. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Improve TX CPU-Tag usageBirger Koblitz2021-10-091-20/+29
| | | | | | | | | On RTL83xx enable learning of the MAC source address of the CPU port from outgoing packets. Add documentation on bit fields. On RTL93xx enable port-mask usage and the use of internal priority, these SoCs automatically learn the MAC. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Remove storm control and attack warningsBirger Koblitz2021-10-091-25/+0
| | | | | | | | Remove the storm control and attack warnings from the IRQ handler of the Ethernet driver. There was no consequence to the detection and the kernel can also handle at least the attacks itself. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Correct TX ring size in ethernet driverBirger Koblitz2021-10-091-2/+1
| | | | | | | This enlarges the size of the TX ring buffer, which prevents warnings when the buffer runs out of space. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: ensure output drivers are enabled in RTL8231Paul Fertser2021-10-021-5/+7
| | | | | | | | | | | | | The bootloader can leave the GPIO expander in a state which doesn't have output drivers enabled so GPIOs will properly work for input but output operations will have no effect. To avoid disrupting the boot in case the bootloader left direction and data registers in an inconsistent state (e.g. pulling SoC's reset to 0) reconfigure everything as input. Reviewed-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
* realtek: fix kernel panic in DSA driver for 5.10INAGAKI Hiroshi2021-09-261-2/+8
| | | | | | | | | | dsa_to_port function in 5.10 returns dsa_port from the port list in dsa_switch_tree, but the tree is built when the switch is registered by dsa_register_switch and it's null in rtl83xx_mdio_probe. So, we need to use dsa_to_port after the registration of the switch. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: fix compile errors in dsa driver for 5.10INAGAKI Hiroshi2021-09-262-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | this patch fixes the following errors when compiling: - dsa_switch_alloc is removed[1] - a parameter "enum dsa_tag_protocol mprot" is added to dsa_tag_protocol in dsa_switch_ops (include/net/dsa.h) - several paramters are added to "phylink_mac_link_up" in dsa_switch_ops (include/net/dsa.h) added: - int speed - int duplex - bool tx_pause - bool rx_pause - a parameter "struct switchdev_trans *trans" is added to port_vlan_filtering in dsa_switch_ops (include/net/dsa.h) [1]: https://lore.kernel.org/lkml/20191020031941.3805884-17-vivien.didelot@gmail.com/ Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* realtek: fix compile errors in rtl838x_eth.c for 5.10INAGAKI Hiroshi2021-09-261-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | this patch fixes the following errors when compiling: - "unsigned int txqueue" is added as an additional parameter of ndo_tx_timeout in net_device_ops (include/linux/netdevice.h) - "mac_link_state" in phylink_mac_ops (include/linux/phylink.h) is renamed to "mac_pcs_get_state" and changed the return value to void from int - several parameters are added to "mac_link_up" in phylink_mac_ops (include/linux/phylink.h) and the order of the parameters is changed added: - int speed - int duplex - bool tx_pause - bool rx_pause - a parameter "phy_interface_t *interface" is added to of_get_phy_mode (drivers/of/of_net.c) and returns the state instead of phy mode Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 23:44:53 +0000