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path: root/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c
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* treewide: remove files for building 5.10 kernelNick Hainke2023-05-121-2064/+0
| | | | | | | | | | | All targets are bumped to 5.15. Remove the old 5.10 patches, configs and files using: find target/linux -iname '*-5.10' -exec rm -r {} \; Further, remove the 5.10 include. Signed-off-by: Nick Hainke <vincent@systemli.org>
* realtek: fix standalone ports in presence of static fdb entriesJan Hoffmann2023-05-071-0/+10
| | | | | | | | | | | | | | | | | | | | The registers L2_PORT_STATIC_MV_ACT seem to specify the action to take when the source address of a packet exists as a static fdb entry on another port. By default the configured action is to drop such packets. For standalone ports, this behaviour is undesired, as all traffic should be forwarded to the CPU. So change the action to forward on standalone ports. A situation where this issue can occur is when a non-offloaded bond interface is part of a bridge. In that case, the CPU port will have fdb entries for devices connected to the bond interface, which are managed by the assisted learning feature. For now, this is only implemented for RTL838x/RTL839x, as the available set of registers differs for the other devices. Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: refactor keep vlan tag setup, fix tagged forwardingLuiz Angelo Daros de Luca2022-12-011-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in dsa.c:rtl83xx_port_enable() was trying to set vlan_port_tag_sts_ctrl while dealing with differences between SoCs. However, not only that register has a different address, the register structure and even the 2-bit value semantic changes for each SoC. The vlan_port_tag_sts_ctrl field was dropped and converted into a vlan_port_keep_incoming_tag_set() function that abstracts the different between SoCs. The macro referencing that register migrated to the SoC specific c file as it will be privately used by each file. All magic numbers were converted into macros using BITMASK and FIELD_PREP. The vlan_port_tag_sts_ctrl debugfs was dropped for now as it is already broken for rtl93xx. The best place for SoC specific code might be in each respective c file and not in if/else clauses. The final result is: rtl838x: set ITAG_STS=TAGGED, same as before rtl839x: set ITAG_STS=TAGGED instead of IGR_P_ITAG_KEEP=0x1, fixing forwarding of tagged packets rtl930x: set EGR_ITAG_STS=TAGGED instead of IGR_P_ITAG=0x1, possibly fixing forwarding of tagged packets rtl931x: set EGR_ITAG_STS=TAGGED instead of OTPID_KEEP=0x1, possibly fixing forwarding of tagged packets Without (EGR_)ITAG_STS=TAGGED, at least for rtl839x, forwarded packets will drop the vlan tag while packets from the CPU will still have the correct tag. Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
* realtek: cleanup rtl83{8x,9x}_enable_learning/floodINAGAKI Hiroshi2022-10-081-21/+11
| | | | | | | | | | | | | In *_enable_learning() only address learning should be configured, so remove enabling forwarding. Forwarding is configured by the respective *_enable_flood() functions. Clean up both functions for RTL838x and RTL839x, and fix the comment on the number of entries. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [squash RTL838x, RTL839x changes] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: rtl838x: Fix ethernet polling timeout on probeOlliver Schinagl2022-09-141-1/+2
| | | | | | | | | | Due to an oversight we accidentally inverted the timeout check. This patch corrects this. Fixes: 9cec4a0ea45b ("realtek: Use built-in functionality for timeout loop") Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> [ wrap poll_timeout line to 80 char ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* realtek: Use built-in functionality for timeout loopOlliver Schinagl2022-09-141-12/+7
| | | | | | | | | | In commit 81e3017609be ("realtek: clean up rtl838x MDIO busy wait loop") a hand-crafted loop was created, that nearly exactly replicate the iopoll's `read_poll_timeout` functionality. Use that instead. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
* realtek: clean up rtl838x MDIO busy wait loopJan Hoffmann2022-07-281-15/+22
| | | | | | | | | | | | | Don't use udelay to allow other kernel tasks to execute if the kernel has been built without preemption. Also determine the timeout based on jiffies instead of loop iterations. This is especially important on devices containing a watchdog with a short timeout. Without this change, the watchdog is not serviced during PHY patching which can take multiple seconds. Tested-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Jan Hoffmann <jan@3e8.eu>
* realtek: Copy all BPDUs to the kernelBirger Koblitz2022-02-171-0/+21
| | | | | | | | In order to receive STP information at the kernel level, we make sure that all Bridge Protocol Data Units are copied to the CPU-Port. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add L2 aging configuration functions for all SoC familiesBirger Koblitz2022-02-171-0/+17
| | | | | | | | Instead of a generic L2 aging configuration function with complex logic, we implement an individual function for all SoC types. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realted: Add DSA bridge offload configurationBirger Koblitz2022-02-171-0/+44
| | | | | | | | Add functionality to enable or disable L2 learning offload and port flooding for RTL83XX. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add Link Aggregation (aka trunking) supportBirger Koblitz2022-02-171-0/+8
| | | | | | | | | This adds LAG support for all 4 SoC families, including support ofr the use of different distribution algorithm for the load- balancing between individual links. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filteringBirger Koblitz2022-02-171-3/+33
| | | | | | | | Use setting functions instead of register numbers in order to clean up the code. Also use enums to define inner/outer VLAN types and the filter type. Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Add SoC-specific routing offload implementationBirger Koblitz2021-10-091-23/+54
| | | | | | | | Adds SoC specific routing offload implementations for RTL8380/90 and RTL9300. RTL83xx supports merely nexthop routing, RTL9300 full host and prefix routes. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Configure initial L2 learning setupBirger Koblitz2021-10-091-0/+19
| | | | | | | | Configure a sane L2 learning configuration upon DSA driver load so that the switch can start learning L2 addresses. Also configure the correct flood masks for broadcast and unknown unicast traffice. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: Packet Inspection Engine support for RTL838x SoCsBirger Koblitz2021-10-091-0/+1007
| | | | | | Adds the RTL838x-specific PIE support routines. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
* realtek: copy config/files/patches to 5.10INAGAKI Hiroshi2021-09-261-0/+859
this patch copies the following files from 5.4 to 5.10: - config-5.4 -> config-5.10 - files-5.4/ -> files-5.10/ - patches-5.4/ -> patches-5.10/ Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [rebase on change in files-5.4] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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