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* lantiq: use new property name for eiu irqsJohn Crispin2016-06-131-1/+1
| | | | Signed-off-by: John Crispin <john@phrozen.org>
* lantiq: Make the ar9.dtsi sram node match "simple-bus"Felix Fietkau2016-01-291-1/+1
| | | | | | | | | | | All other SoC types are using "lantiq,sram" and "simple-bus" to ensure that all child nodes are set up correctly during linux kernel initialization (plat_of_setup(void) in arch/mips/lantiq/prom.c). Without this some of sram child nodes might not be parsed. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48548
* lantiq: Switch to the new SPI driverFelix Fietkau2016-01-171-1/+3
| | | | | | | | | | | | | | | | Compared to the "old" driver: - Each device must assign a pinctrl setting to the SPI node to allow the new SPI driver to configure the SPI pins. While here we are also using separate input and output settings so we are independent of whether the bootloader configures the pins correctly. - We use the new "compatible" strings to make the driver choose the correct number of chip-selects for each SoC. - The new driver starts counting the chip-selects at 1 (instead of 0, like the old one did). Thus we have to adjust the devices accordingly. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48293
* lantiq: Add the SPI node to ar9.dtsi and vr9.dtsiFelix Fietkau2016-01-171-0/+10
| | | | | | | | | | This allows devices to use SPI without having to re-define (and thus duplicating) the whole SPI node. By default SPI is disabled (as before) because only few devices need it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48286
* lantiq: Use the new pinctrl compatible stringsFelix Fietkau2016-01-171-1/+1
| | | | | | | | | | | | | | | | These were introduced in upstream commit be14811c03cf "pinctrl/lantiq: introduce new dedicated devicetree bindings" and finally allow us to use the individual pins within our dts (for example spi_clk, etc.). Please note that this changes the number of GPIOs which are available for some SoCs. VRX200 SoCs for example only have 50 pins, but previously 56 pins were exposed. This means that all places which are using hardcoded GPIO numbers (which are not passed via device-tree) need to be adjusted (because the first GPIO number is now 462, instead of 456). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48284
* lantiq: Introduce DWC2 compatible DTS definitions for AR9 USBJohn Crispin2015-09-141-1/+10
| | | | | | | | | | | | Since the AR9 USB is very similar to the VR9 USB it too can be used with the upstream DWC2 driver. Here are the DTS definitions which make it compatible with the DWC2 driver. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> SVN-Revision: 46914
* lantiq: add 3.18 supportJohn Crispin2015-02-091-0/+4
| | | | | | Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44348
* lantiq: move dts files to thir own folderJohn Crispin2013-04-251-0/+179
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 36443
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