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path: root/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
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* ipq806x: drop linux 4.9 supportStefan Lippers-Hollmann2018-05-241-415/+0
| | | | | Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> (cherry picked from commit 2819732219904a81205abe0fa3fbe9c06884f119)
* ipq806x: remove rpm pinctrl from board dtsPavel Kubelun2018-05-241-5/+0
| | | | | | | | | | | These pins seem to be used by hw exclusively, so claiming it in kernel causes an error in syslog in k4.14+. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> [slh: rebase for kernel v4.14 as well] Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> (cherry picked from commit 96cd31655d3de9078036ff74562ee50ef8724318)
* ipq806x: fix EA8500 switch controlPavel Kubelun2018-05-241-4/+18
| | | | | | | | | | | | | | | | | | | EA8500 has pcie2 slot unequipped. By EA8500 hw design default pcie2 reset gpio (gpio63) is used to reset the switch. That's why enabling pcie2 brings the switch into a working state. So let's just control the gpio63 without enabling the pcie2 slot. We have to remove the pcie2_pins node so the gpio63 is not defined twice. Because pcie2 node has a reference to pcie2_pins we have to remove it as well. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> [slh: rebase for kernel v4.14 as well] Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> (cherry picked from commit 7f694ef3d9f1121c03935c330093c594b8437098)
* ipq806x: move mass market ipq8064 to v2 dtsiPavel Kubelun2018-05-241-1/+1
| | | | | | | | | | | | | | | | | | | According to OEM bootlog entry mass market devices are ipq8064 SoC v2.0: > socinfo_init: v6, id=202, ver=2.0, raw_id=2064, raw_ver=2064, hw_plat=0, hw_plat_ver=65536 I've checked C2600, EA8500 and VR2600v but couldn't find other boards bootlog. I think it's safe to assume that other boards are also v2.0. R7500 may be an exception because it was the first device to hit the market. So switch to v2.0 dtsi. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> [slh: rebase for kernel v4.14 as well] Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> (cherry picked from commit 067036e8750a61a700718bf874e52b18a11cb277)
* ipq806x: force 2nd pci slot into gen1 modePavel Kubelun2018-01-171-5/+3
| | | | | | | | | | | | | | According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode. EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode. In previous commit we've added the support for this option, so enable it in DT for affected devices. QSDK ref: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506 While at it move the phy transmit termination offset value into dtsi file as it's platform specific. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
* ipq806x: fix NAND support for linux 4.9Felix Fietkau2017-03-131-104/+113
| | | | Signed-off-by: Felix Fietkau <nbd@nbd.name>
* ipq806x: clean up dts patchFelix Fietkau2017-03-081-0/+399
Move dts files to files/, remove useless patch chunks Signed-off-by: Felix Fietkau <nbd@nbd.name>