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Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
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These pins seem to be used by hw exclusively, so claiming it in
kernel causes an error in syslog in k4.14+.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
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According to OEM bootlog entry mass market devices are ipq8064 SoC
v2.0:
> socinfo_init: v6, id=202, ver=2.0, raw_id=2064, raw_ver=2064, hw_plat=0, hw_plat_ver=65536
I've checked C2600, EA8500 and VR2600v but couldn't find other
boards bootlog. I think it's safe to assume that other boards are
also v2.0. R7500 may be an exception because it was the first
device to hit the market.
So switch to v2.0 dtsi.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
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According to QSDK and OEM tarballs (checked c2600, r7500v2, r7800) 2nd pci slot (pci1, 2,4 GHz card)) on ap148 based boards should operate in gen1 mode.
EA8500 is an exception and according to GPL pcie0 should operate in gen1 mode.
In previous commit we've added the support for this option, so enable it in DT for affected devices.
QSDK ref:
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?h=release/endive_preview_cc&id=f3b07fe309027c52fc163149500cedddd707c506
While at it move the phy transmit termination offset value into dtsi file as it's platform specific.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
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Move dts files to files/, remove useless patch chunks
Signed-off-by: Felix Fietkau <nbd@nbd.name>
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